Senior SoC/IP Verification Lead - Build & Mentor Teams

NanoXplore SAS; Sèvres; Sur place; EUR 90 000 - 130 000; Plein temps

Avantages offerts par ce poste

Growth opportunities

Competitive package

Employee development

Well-being

Résumé du poste

NanoXplore is seeking a SoC/IP Verification Lead Engineer in the Paris region (Sèvres) or Meylan to drive verification strategy for complex SoCs and IPs. You will build and mentor a high-performing verification team, collaborating with Architecture, Design, and other Hardware R&D colleagues to define verification plans and ensure product reliability.

The role requires strong SystemVerilog/UVM expertise, RTL/VHDL knowledge, and leadership experience.

Qualifications

• Strong experience in SoC and IP verification methodologies and tools.
• Proven track record in writing verification and test plans.
• Extensive experience with SystemVerilog, UVM, Testbench development, C-based test cases.

Responsabilités

• Build, structure, and grow the verification team.
• Recruitment, onboarding, mentoring, and technical coaching.
• Define, write, review, and maintain verification strategies and plans.
• Develop advanced verification environments and testbenches.
• Execute simulations, analyze results, and debug complex SoC and IP designs.
• Ensure verification coverage and product reliability.
• Drive continuous improvement of processes, tools and methodologies.
• Guide verification engineers on complex technical challenges.
• Contribute to methodology decisions and verification roadmap.
• Act as a technical reference within Hardware R&D.

Connaissances

SystemVerilog

UVM

Testbenches

C-based tests

RTL verification

VHDL

UPF

DFT concepts

Formal verification

Python

Tcl

Shell scripting

ARM-based systems

PCIe

Ethernet

DDR4/DDR5

Trace & debug

Formation

Master’s degree in Electronics/Computer Engineering

Outils

SystemVerilog

UVM

Description du poste

NanoXplore is seeking a SoC/IP Verification Lead Engineer in the Paris region (Sèvres) or Meylan to drive verification strategy for complex SoCs and IPs. You will build and mentor a high-performing verification team, collaborating with Architecture, Design, and other Hardware R&D colleagues to define verification plans and ensure product reliability.

The role requires strong SystemVerilog/UVM expertise, RTL/VHDL knowledge, and leadership experience.