Senior Digital Implementation Engineer: SoC Timing

TDK InvenSense; Grenoble; Sur place; EUR 70 000 - 100 000; Plein temps

Résumé du poste

InvenSense, a TDk group company, is seeking top-notch engineers to join our global team, helping us grow to become a leading provider of MEMS and SoC platform solutions for mobile, industrial, and automotive markets.

You will implement and improve digital blocks in analog-on-top products, drive block timing closure, STA and clock-network guidelines, and collaborate with RTL and Physical-design teams across an international environment from RTL to GDS.

Qualifications

• 5+ years in Synthesis and Timing closure with STA and Signal-Integrity analysis.
• Strong HDL knowledge and experience interfacing RTL and Physical teams.
• Experience with DFT/ATPG is a plus.

Responsabilités

• Generate block level timing constraints with RTL/DFT teams.
• Run Logical/Physical synthesis and Formal Verification; develop clock network guidelines.
• Interface with Physical-Design for block closure.
• Create constraints for chip level timing closure; drive ECO loops.
• Perform STA at block and chip level and provide guidance for STA-Signoff.
• Develop and maintain methodologies and flows.

Connaissances

Synthesis & Timing closure

STA (Timing closure)

Clock network guidelines

Verilog HDL

DFT & ATPG

MMMC

OCV

Power/low power design (UPF/CPF)

Scripting (Tcl/Perl/CShell)

Outils

Synopsys tools

Description du poste

InvenSense, a TDk group company, is seeking top-notch engineers to join our global team, helping us grow to become a leading provider of MEMS and SoC platform solutions for mobile, industrial, and automotive markets.

You will implement and improve digital blocks in analog-on-top products, drive block timing closure, STA and clock-network guidelines, and collaborate with RTL and Physical-design teams across an international environment from RTL to GDS.