MEMS - Digital Verification - SR/Team Leader

STMicroelectronics France; Toulouse; On-site; EUR 40,000 - 65,000; Full time

Job summary

STMicroelectronics France is seeking a Digital Verification Engineer in Toulouse. The ideal candidate has 3-5 years of experience in digital verification of ASICs, responsible for defining test benches and developing components. You will work closely with the MEMS Group, utilizing skills in System Verilog and UVM. Strong communication and collaboration abilities are essential. The position fosters a diverse and inclusive workplace, aiming for equity in career development.

Qualifications

• 3-5 years of experience in digital verification of ASICs.
• Proficiency in verification components and test case development.
• Good team collaboration and fluency in English.

Responsibilities

• Define and develop verification testbench.
• Develop verification components and DSP models.
• Create test cases for simulation and debug failures.

Skills

Digital verification testbench

Universal Verification Methodology

System Verilog

Digital simulator tools

Python scripts

TCL scripts

Version control systems

Formal verification

Communication protocols (I2C, SPI, I3C)

Good communication skills

Job description

YOUR ROLE

The position is for a Digital Verification Engineer with 3-5 years of experience in digital verification of ASICs. The candidate will be part of the digital verification team of the MEMS Group and will follow the entire ASIC verification process from specification definition to final product industrialization.

RESPONSIBILITIES

• Definition and development of verification testbench.
• Development of verification components.
• Development of DSP models and digital control logic.
• Test case development for simulation.
• Debugging failures and creating simulation cases for various scenarios.

QUALIFICATIONS AND SKILLS

• Background in digital verification testbench (Universal Verification Methodology and System Verilog).
• Experience with digital simulator tools.
• Proficiency in System Verilog, UVM, System Verilog Assertion, coverage, self-checking capabilities, testbench automation, bug analysis and reporting.
• Basic knowledge of Python scripts, TCL scripts, and version control systems.
• Knowledge of formal verification and communication protocols (e.g., I2C, SPI, I3C) is a plus.
• Good communication skills; fluent in English; team player with strong collaboration across the MEMS Group Design team.

EEO STATEMENTS

At ST, we endeavor to foster a diverse and inclusive workplace, and we do not tolerate discrimination. We aim to recruit and retain a diverse workforce that reflects the societies around us. We strive for equity in career development, career opportunities, and equal remuneration.