Digital Physical Implementation Expert

MELEXIS; Paris; Hybrid; EUR 70,000 - 90,000; Full time

Benefits offered by this job

Competitive salary

Comprehensive benefits package

Continuous learning opportunities

Hybrid way of working

Job summary

MELEXIS is currently looking for a Digital Physical Implementation Expert to enhance our automotive product development in Paris. The role encompasses leading the physical design implementation from RTL to GDSII, requiring a thorough understanding of design for manufacturability and experience with Cadence EDA tools.

This position offers an exciting challenge in a high-tech environment, focusing on semiconductor products. Ideal candidates will have solid experience in Static Timing Analysis and mixed-signal integration.

We offer a competitive salary, benefits, and opportunities for professional development in a collaborative team culture with a focus on diversity and inclusion.

Qualifications

• 7+ years of relevant working experience.
• Expertise in Static Timing Analysis (STA) principles.
• Experience with complex floorplans.

Responsibilities

• Lead the physical design implementation from RTL to GDSII.
• Complex floor planning and power planning.
• Design effective clock distribution networks.

Skills

Static Timing Analysis (STA)

Cadence EDA tools

Complex floorplanning

Power Integrity

Digital Physical Implementation

Education

PhD or master's degree in microelectronics

Tools

Cadence Innovus

Tcl

Python

Job description

We are seeking a skilled and experienced Digital Physical Implementation Expert to join our Digital Competence Center, operating within a mixed-signal environment and focusing mostly but not only limited on our automotive products. In this role, you will be responsible for the complete physical design implementation from RTL to GDSII, transforming complex logical designs into high-performance, power-efficient, and manufacturable physical layouts for advanced automotive-grade semiconductor chips.

You will possess a good understanding of the overall physical implementation flow, demonstrate expert-level proficiency in Static Timing Analysis (STA), and be adept at handling complex floorplans within a mixed-signal context. Your understanding of RTL code, coupled with your ability to minimize both EMC emission and power consumption especially for clock trees, will be key competencies in your daily activities. You will be able to contribute significantly to the development and improvement of our physical design flow. Your practical experience and comfort with Cadence EDA tools will be essential as you navigate the requirements of automotive standards, mixed-signal integration, and contribute to the successful physical realization of our innovative products.

More specifically, you will:

• Lead the complete physical design implementation of digital blocks from RTL to GDSII within complex mixed-signal integrated circuits destined for automotive applications, ensuring optimal PPA (Power, Performance, Area) targets are met while adhering to automotive quality and reliability standards.

• Complex Floor planning and Power Planning: Developing intricate layouts for digital blocks within a mixed‑signal chip, strategically placing digital logic and defining robust power distribution networks while meticulously considering noise isolation from analog sections and overall system‑level performance for automotive environments.
• Placement: Performing highly optimized placement of standard cells, digital macros, and digital IP blocks, with careful consideration for timing, power, congestion, and the digital-analog interface.
• Clock Tree Synthesis (CTS): Designing and implementing highly effective clock distribution networks for digital logic, with an unwavering focus on minimizing both Electro‑Magnetic Compatibility (EMC) emission and power consumption of clock trees, while also minimizing clock coupling and noise impact on sensitive analog circuits.
• Routing: Executing global and detailed routing for digital signals, ensuring strict adherence to design rules, maintaining signal integrity, minimizing crosstalk, and optimizing critical paths within digital blocks and across mixed‑signal interfaces.

• Act as an expert in Static Timing Analysis (STA), proactively identifying, debugging, and resolving complex timing issues within digital blocks and across digital-analog interfaces to achieve timing closure for challenging automotive designs across various operating corners and conditions by cooperating with digital Front-End and mixed-signal engineers.
• Conduct and debug EMIR (Electro-Migration and IR Drop) verification to ensure power integrity and reliability of the digital blocks.
• Apply Design for Manufacturability (DFM) principles throughout the physical implementation process to enhance yield and reliability for automotive production.
• Demonstrate a good understanding of RTL code (Verilog) for effective analysis, debugging, and collaboration with frontend teams.
• Able to contribute significantly to the development, enhancement, and optimization of the physical design flow, identifying bottlenecks and implementing solutions to improve efficiency and quality in cooperation with other Physical Implementation engineers.
• Work closely with frontend design, analog design, architects, DFT (Design for Test), and CAD teams to ensure seamless integration, effective hand-offs between digital and analog domains, and accurate timing constraints for automotive mixed-signal designs.
• Utilize and contribute to the development of automation scripts (e.g., Tcl, Python, Perl) to enhance design efficiency, particularly for digital physical implementation tasks and STA analysis, leveraging your comfort with Cadence tools.
• Collaborate with and provide technical support to team members as needed, sharing insights on mixed-signal integration, low-power, EMIR, and DFM best practices.

Your profile

• Engineering PhD or master degree in microelectronics, and you have at least 7 years of relevant working experience.
• Expert-level proficiency in Static Timing Analysis (STA) principles and methodologies, with extensive practical experience in analyzing and closing timing for complex digital blocks within mixed-signal designs.
• Proven experience with complex floorplans for digital blocks within mixed-signal ICs, including handling sensitive analog interfaces.
• Strong understanding of RTL code (Verilog) for effective analysis, debugging, and collaboration with frontend teams.
• Ability to contribute to and improve physical design flows.
• Comfortable and proficient with Cadence EDA tools for physical design and STA, such as Innovus, Genus, Tempus, Voltus, Comformal, Pegasus, Quantus...
• Experience with scripting languages (Tcl, Python) for automation.
• Solid understanding of semiconductor manufacturing processes and digital design rules.
• Superior problem-solving skills and ability to debug complex physical design issues, particularly those arising from mixed-signal integration, EMC, power integrity, EMIR, and DFM.
• Strong communication and interpersonal skills, with the ability to work effectively in a collaborative team environment.
• Experience with custom analog layout considerations and their interaction with digital physical design.

We offer

• A competitive salary and comprehensive benefits package.
• A challenging job in a dynamic high‑tech and multi‑cultural environment.
• The opportunity to work on challenging mixed‑signal IC projects that are critical to the automotive and industrial sectors, directly impacting future vehicle technology.
• The possibility to take ownership of your professional passion in order to contribute to the success of the company.
• A team‑oriented and professional atmosphere in a flat‑structured organisation with a people‑first culture.
• Continuous learning and professional development opportunities.
• Hybrid way of working.

Diversity & Inclusion

Melexis is an Equal Opportunity Employer that values and respects the importance of a diverse and inclusive workforce. It is the policy of the company to recruit, hire, train and promote persons in all job titles without regard to race, colour, religion, sex, age, national origin, veteran status, disability, sexual orientation, or gender identity. We recognize that diversity and inclusion is a driving force in the success of our company.