Senior Digital IC Backend Architect (PPA & Tapeout)

Arago Inc.; Paris; Sur place; EUR 90 000 - 130 000; Plein temps

Avantages offerts par ce poste

Competitive cash compensation

Meaningful stock option plan

Relocation bonus

Healthcare coverage

25 days of PTO

Résumé du poste

A forward-thinking AI company in Paris is looking for a Digital Backend Design Engineer to implement digital designs from RTL to GDSII. The candidate should have a Master's or PhD in Electrical Engineering and at least 4 years of experience. Proficiency in Cadence tools and Tcl scripting is essential. The role offers competitive pay, stock options, and a dynamic multicultural environment with opportunities for growth.

Qualifications

• 4+ years experience in digital IC backend implementation.
• Experience with advanced technology nodes (22nm or below preferred).
• Solid grasp of static timing analysis (STA), DRC/LVS verification, IR drop, and electromigration (EM) analysis.

Responsabilités

• Execute full-chip and block-level physical design tasks including floorplanning, placement, clock tree synthesis, routing, and verification.
• Develop and optimize digital backend flows.
• Support tapeout preparation and final signoff processes.

Connaissances

Backend EDA tools proficiency

Tcl scripting for automation

Strong understanding of P&R

Experience in hierarchical or full-chip implementation

Formation

Master’s or PhD in Electrical/Electronic Engineering

Outils

Cadence Innovus

Cadence Genus

Description du poste

A forward-thinking AI company in Paris is looking for a Digital Backend Design Engineer to implement digital designs from RTL to GDSII. The candidate should have a Master's or PhD in Electrical Engineering and at least 4 years of experience. Proficiency in Cadence tools and Tcl scripting is essential. The role offers competitive pay, stock options, and a dynamic multicultural environment with opportunities for growth.