Senior ASIC Physical Implementation Engineer for IP/eFPGA

Menta SAS; Valbonne; On-site; EUR 50,000 - 80,000; Full time

Job summary

A technology firm specializing in ASIC design in Valbonne is seeking an experienced professional for ASIC physical implementation of eFPGA IP architectures. You will lead efforts from RTL to GDSII and improve internal design flows. Ideal applicants should have at least 5 years of relevant experience, strong communication skills, and proficiency in Synopsys and scripting tools. A Master's in Electrical Engineering is required. Join a challenging role within a dynamic, innovative team.

Qualifications

• 5 years of relevant experience in ASIC physical implementation.
• Good written and spoken English is mandatory.
• Experience on advanced technology nodes (28nm, 22nm, 12nm and below) is a plus.

Responsibilities

• In charge of ASIC physical implementation of eFPGA IP architectures.
• Contribute to the development and maintenance of internal design flow.
• Work in a dynamic environment with cross-functional teams.

Skills

ASIC physical implementation

Digital back-end EDA tool flows

Knowledge of Synopsys tools

C++ programming

Scripting languages (Tcl, Python, bash)

RTL design (VHDL, Verilog, SystemVerilog)

Education

MSc in Electrical Engineering or equivalent

Tools

Synopsys tools (DC, ICC2, Primetime)

Cadence tools

Siemens-Calibre

Job description

A technology firm specializing in ASIC design in Valbonne is seeking an experienced professional for ASIC physical implementation of eFPGA IP architectures. You will lead efforts from RTL to GDSII and improve internal design flows. Ideal applicants should have at least 5 years of relevant experience, strong communication skills, and proficiency in Synopsys and scripting tools. A Master's in Electrical Engineering is required. Join a challenging role within a dynamic, innovative team.