Physical Implementation Engineer

Menta SAS; Valbonne; Sur place; EUR 50 000 - 80 000; Plein temps

Résumé du poste

A technology firm specializing in ASIC design in Valbonne is seeking an experienced professional for ASIC physical implementation of eFPGA IP architectures. You will lead efforts from RTL to GDSII and improve internal design flows. Ideal applicants should have at least 5 years of relevant experience, strong communication skills, and proficiency in Synopsys and scripting tools. A Master's in Electrical Engineering is required. Join a challenging role within a dynamic, innovative team.

Qualifications

• 5 years of relevant experience in ASIC physical implementation.
• Good written and spoken English is mandatory.
• Experience on advanced technology nodes (28nm, 22nm, 12nm and below) is a plus.

Responsabilités

• In charge of ASIC physical implementation of eFPGA IP architectures.
• Contribute to the development and maintenance of internal design flow.
• Work in a dynamic environment with cross-functional teams.

Connaissances

ASIC physical implementation

Digital back-end EDA tool flows

Knowledge of Synopsys tools

C++ programming

Scripting languages (Tcl, Python, bash)

RTL design (VHDL, Verilog, SystemVerilog)

Formation

MSc in Electrical Engineering or equivalent

Outils

Synopsys tools (DC, ICC2, Primetime)

Cadence tools

Siemens-Calibre

Description du poste

You will be in charge of doing the ASIC physical implementation of eFPGA IP architectures.

Within the Hardware Physical Implementation team, you will be in charge of doing the ASIC physical implementation of eFPGA IP architectures (from RTL to GDSII) to bring them into production.

You will also contribute to the development, improvement and maintenance of our internal design flow.

This is a challenging position and an opportunity to work within a small but highly qualified team. You will get the chance to work on one of the most exciting new semiconductor products and on the most advanced process nodes (from 180nm to 5nm and beyond).

Skills & Experience

• 5 years of relevant experience in ASIC physical implementation
• Knowledge of digital back-end EDA tool flows: Synthesis, Place and Route, STA, Formal-Verification and Signoff checks (LVS/DRC/ERC/EM-IR/…)
• Knowledge of Synopsys tools (DC, ICC2, Primetime, StarRC, etc.) is a must. Knowledge of Siemens-Calibre and Cadence tools are a plus
• Experience at IP level and IP integration at top level
• Knowledge of Power-management concepts is a plus
• Experience on advanced technology nodes, such as 28nm, 22nm, 12nm and below is a plus
• Experience with C++, make files and scripting languages such as Tcl, Python and bash
• Technical background in RTL design (VHDL, Verilog, SystemVerilog) and/or RTL synthesis is a plus
• Good listening and communication skills
• Self-reliant and solid team player skills
• Good analytical and problem-solving skills
• Good written and spoken English is mandatory
• MSc in Electrical Engineering or equivalent

The candidate will work in a dynamic environment and will get to work with teams from different technical areas in which new creative and innovative ideas will be much appreciated

MENTA’s technology offers a highly reliable solution for all those involved in innovation, thanks to its high degree of customization to different technologies and customer needs, the performance and durability it offers to electronic chips, combined with unbeatable production times.

Our vision is one of responsible progress, fueled by a pioneering spirit of excellence and self-improvement, creating value.
Accelerating progress through our technologies means meeting the challenges of the future together.

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