R&D Hardware Engineer: Memory Architecture & GEM5

European Tech Recruit; Paris; Sur place; EUR 45 000 - 65 000; Plein temps

Avantages offerts par ce poste

CDD through July 2027

Résumé du poste

European Tech Recruit is seeking an R&D Engineer - Hardware Design / Memory Architecture in Paris to join a global tech team developing next-generation processor and memory architectures. You will research and develop a memory monitor for many-core systems using GEM5, SystemC or RTL, then integrate it with the operating system through a driver.

The role spans hardware modelling and low-level software, evaluating memory-management approaches through simulation and experimentation.

Qualifications

• BSc, MSc or PhD in Computer Engineering, Computer Science, Electronics or related field.
• Experience with RTL, GEM5 or SystemC.
• Strong C or C++ programming.
• Knowledge of computer architecture and memory systems.
• Understanding of OS concepts and/or driver development.
• Knowledge of memory/cache coherence.
• Many-core/multicore, RISC-V or SoC experience.
• Distributed shared memory or chip interconnect knowledge.
• Python for simulation/data analysis.
• Research experience and at least one first-author paper.

Responsabilités

• Develop and model a memory monitor for many-core architectures.
• Use GEM5, SystemC or RTL to prototype and evaluate hardware concepts.
• Investigate memory behaviour and shared-memory architectures.
• Develop OS drivers connecting hardware and software.
• Run simulations, analyse results and contribute to research publications.

Connaissances

C/C++ programming

Computer architecture

OS concepts & driver development

Python for simulation/data analysis

Formation

BSc/MSc/PhD in Computer Engineering/CS/Electronics

Outils

RTL

GEM5

SystemC

Description du poste

European Tech Recruit is seeking an R&D Engineer - Hardware Design / Memory Architecture in Paris to join a global tech team developing next-generation processor and memory architectures. You will research and develop a memory monitor for many-core systems using GEM5, SystemC or RTL, then integrate it with the operating system through a driver.

The role spans hardware modelling and low-level software, evaluating memory-management approaches through simulation and experimentation.