Hardware Software Design Engineer

European Tech Recruit; Paris; Sur place; EUR 90 000 - 130 000; Plein temps

Résumé du poste

European Tech Recruit seeks a Hardware/Software Co-Design Engineer for a contract in Paris, running until 30 July 2027. The role targets memory management optimization and advanced computer architecture research.

You will simulate memory models with GEM5, prototype memory-coherence techniques, and develop the OS layer to enable IPC within the memory model, plus run experiments and publish results.

Qualifications

• Experience with memory systems and HPC architectures.
• Proficiency in C/C++ programming.
• Hands-on GEM5 and memory-model experience.

Responsabilités

• Simulate memory architectures for HPC using GEM5.
• Prototype OS layer to enable IPC within the memory model.
• Run experiments, plot data, and prepare results for publication.
• Evaluate impact of memory atomic operations in distributed shared memory.

Connaissances

High-performance computing

Problem solving

Research experience

Outils

GEM5 simulator

Memory architectures

Memory coherence

C/C++ programming

Description du poste

Hardware/Software Co-Design Engineer | Memory Architecture / GEM5 / OS Layer

A global leader in telecommunications and technology is seeking a specialized Engineer for a contract role running up to 30th July 2027. This position focuses on HW/SW Codesign for Memory Management Optimization and offers the opportunity to work at the cutting edge of computer architecture and publication-grade research.

The Role

The successful engineer will focus on simulating and optimizing memory architectures for high-performance computing. Responsibilities include simulating many-core models with a focus on memory management using the GEM5 simulator, as well as prototyping and evaluating the impact of memory atomic operations in distributed shared memories. On the software side, the role involves developing the OS layer to enable seamless inter-process communication within the memory model, alongside running experiments, plotting data, and analyzing results for potential industry publications.

Technical Requirements

• Proven hands-on experience utilizing the GEM5 simulator.
• Deep, fundamental knowledge of memory architectures and how they are managed by the OS.
• A detailed, expert-level understanding of memory coherence.
• High proficiency in C or C++ programming.

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