Research And Development Engineer

European Tech Recruit; Paris; Sur place; EUR 45 000 - 65 000; Plein temps

Avantages offerts par ce poste

CDD through July 2027

Résumé du poste

European Tech Recruit is seeking an R&D Engineer - Hardware Design / Memory Architecture in Paris to join a global tech team developing next-generation processor and memory architectures. You will research and develop a memory monitor for many-core systems using GEM5, SystemC or RTL, then integrate it with the operating system through a driver.

The role spans hardware modelling and low-level software, evaluating memory-management approaches through simulation and experimentation.

Qualifications

• BSc, MSc or PhD in Computer Engineering, Computer Science, Electronics or related field.
• Experience with RTL, GEM5 or SystemC.
• Strong C or C++ programming.
• Knowledge of computer architecture and memory systems.
• Understanding of OS concepts and/or driver development.
• Knowledge of memory/cache coherence.
• Many-core/multicore, RISC-V or SoC experience.
• Distributed shared memory or chip interconnect knowledge.
• Python for simulation/data analysis.
• Research experience and at least one first-author paper.

Responsabilités

• Develop and model a memory monitor for many-core architectures.
• Use GEM5, SystemC or RTL to prototype and evaluate hardware concepts.
• Investigate memory behaviour and shared-memory architectures.
• Develop OS drivers connecting hardware and software.
• Run simulations, analyse results and contribute to research publications.

Connaissances

C/C++ programming

Computer architecture

OS concepts & driver development

Python for simulation/data analysis

Formation

BSc/MSc/PhD in Computer Engineering/CS/Electronics

Outils

RTL

GEM5

SystemC

Description du poste

R&D Engineer - Hardware Design / Memory Architecture

Paris, France, Onsite, Fixed-Term Contract (CDD)

Join the R&D team of a global technology company developing next-generation processor and memory architectures. As an R&D Engineer - Hardware Design / Memory Architecture, you will research and develop a memory monitor for many-core systems using GEM5, SystemC or RTL, then integrate it with the operating system through a driver.

The R&D Engineer - Hardware Design / Memory Architecture will work across hardware modelling and low-level software, evaluating new memory-management approaches through simulation and experimentation.

Key Responsibilities

• Develop and model a memory monitor for many-core architectures.
• Use GEM5, SystemC or RTL to prototype and evaluate hardware concepts.
• Investigate memory behaviour and shared-memory architectures.
• Develop OS drivers connecting hardware and software.
• Run simulations, analyse results and contribute to research publications.

Required Experience & Skills

• BSc, MSc or PhD in Computer Engineering, Computer Science, Electronics or related field.
• Experience with RTL, GEM5 or SystemC.
• Strong C or C++ programming.
• Knowledge of computer architecture and memory systems.
• Understanding of OS concepts and/or driver development.
• Knowledge of memory/cache coherence.
• Many-core/multicore, RISC-V or SoC experience.
• Distributed shared memory or chip interconnect knowledge.
• Python for simulation/data analysis.
• Research experience and at least one first-author paper.

Why Apply?

• Work on next-generation processor and memory architectures.
• Genuine HW/SW co-design across hardware and OS.
• Hands-on GEM5/SystemC and computer architecture research.
• Opportunity to contribute to potential publications.
• Open to strong MSc graduates and early-career engineers.
• CDD initially through July 2027, with potential extension.

Recruiter's Note

Ideal candidates include Computer Architecture Engineers, Hardware Engineers, SoC Engineers, HW/SW Co-Design Engineers and Research Engineers with GEM5, SystemC or RTL experience. Candidates from semiconductor, processor design, embedded, HPC or academic research environments are particularly relevant. Memory systems, cache coherence and OS driver experience will differentiate strong candidates.