Memory Design Lead - Embedded Compiler for SoCs

Silvaco Inc; Montbonnot-Saint-Martin; Hybride; EUR 120 000 - 180 000; Plein temps

Résumé du poste

Silvaco Inc. in France seeks a Memory Design Lead to drive architecture, design and delivery of embedded memory compilers for SRAM, ROM, and RAM variants. You will lead a team, shape cross-node technology decisions, and partner with customers from presales to silicon qualification.

Strong memory compiler and RTL experience are required. You will mentor engineers, manage roadmaps, and own PPA-focused optimization while ensuring robust design reviews and signoff processes.

Qualifications

• BS/MS/PhD in Electrical Engineering or related field with strong memory design background.
• 10+ years embedded memory design experience with production tapeouts.
• Expertise in bitcell design, peripherals, and memory compilers.
• Experience across multiple nodes and RTL/Verilog modeling.
• Strong customer-facing and presales capabilities.

Responsabilités

• Lead architecture, design, and physical implementation of memory compilers.
• Define bitcell, peripheral architecture, and redundancy strategies for PPA targets.
• Drive Vmin, leakage, performance, area, and yield across corners.
• Own the memory portfolio roadmap and methodology for verification and signoff.
• Lead silicon validation, test chip development, and customer engagements.

Connaissances

Memory design

Team leadership

Presales

SPICE

Verilog

Python

Customer engagement

Formation

BS/MS/PhD in Electrical Engineering

Outils

Tessent

FastScan

RedHawk

DRC/LVS

GDSII

Verilog

Python

Description du poste

Silvaco Inc. in France seeks a Memory Design Lead to drive architecture, design and delivery of embedded memory compilers for SRAM, ROM, and RAM variants. You will lead a team, shape cross-node technology decisions, and partner with customers from presales to silicon qualification.

Strong memory compiler and RTL experience are required. You will mentor engineers, manage roadmaps, and own PPA-focused optimization while ensuring robust design reviews and signoff processes.