Principal Hardware Architect

IC Resources; Île-de-France; Sur place; EUR 65 000 - 100 000; Plein temps

Résumé du poste

IC Resources is seeking a Principal SoC / NoC Architect – Cache Coherency in France to define cache coherency architectures and scalable interconnects for multi-core, chiplet-based systems. You will shape NoC architectures and PPA targets while collaborating across hardware, software, product, and customers.

Work with CHI, UCIe, PCIe and UA Link to optimise latency, bandwidth and power. This role offers a Europe-wide scope with a market salary and EU work rights preferred.

Qualifications

• Strong experience in cache coherency and SoC/NoC architectures.
• Proven expertise with memory hierarchy design and interconnect protocols.
• Familiarity with CHI, UCIe, PCIe and chiplet-based systems.

Responsabilités

• Define cache coherency architectures for complex SoCs.
• Develop scalable coherent interconnects for multi-core and chiplet systems.
• Work on NoC architecture and microarchitecture, optimizing latency, bandwidth, power and area.

Connaissances

Cache Coherency

SoC Architecture

NoC Architecture

Memory Hierarchies

CHI

UCIe

PCIe

Chiplets

Interconnect

RTL

Description du poste

Principal SoC / NoC Architect – Cache Coherency

France | €65,000–€100,000 | SoC / NoC / Chiplets / CHI / UCIe

Want to work on the architecture behind some of the world’s most advanced SoCs and chiplet-based systems?

I’m working with a global semiconductor IP company whose technology is used by leading chip companies to build high-performance, power-efficient SoCs.

They are now looking for a Principal Hardware Architect / Cache Coherency Architect to help define and evolve next-generation cache-coherent Network-on-Chip IP.

What you’ll work on

• Define cache coherency architectures for complex SoCs
• Develop scalable coherent interconnect solutions for multi-core and chiplet systems
• Work on NoC architecture and microarchitecture
• Optimise latency, bandwidth, power and area
• Define PPA targets for configurable IP
• Work with technologies including CHI, UCIe, PCIe and UA Link
• Support verification and emulation teams on coherency behaviour
• Work across hardware, software, product and customer-facing teams
• Influence future interconnect and chiplet architecture

What we’re looking for

Strong experience in:

• Cache Coherency
• SoC Architecture
• NoC Architecture
• Memory Hierarchies
• CHI
• UCIe
• PCIe
• Chiplets
• Interconnect
• RTL

You may currently be working as:

• SoC Architect
• NoC Architect
• Cache Coherency Architect
• Principal Hardware Architect
• Senior ASIC Design Engineer moving into architecture

Why this one stands out

This company operates right at the centre of one of the biggest challenges in modern semiconductor design: how increasingly complex processors, accelerators, memory systems and chiplets communicate efficiently.

You’ll work on commercially deployed IP used in advanced semiconductor products, while solving genuinely difficult problems in coherency, interconnect and system architecture.

Salary: €65,000–€100,000 baseLocation: FranceEligibility: Existing EU work rights preferred