Cache Coherency Architect — High-Performance NoC IP

Arteris; Biot; Sur place; EUR 80 000 - 110 000; Plein temps

Résumé du poste

A leading semiconductor solutions provider in Provence-Alpes-Côte d'Azur is seeking a Cache Coherency Architect to design high-performance cache coherency solutions. This role involves collaboration with hardware, software, and verification teams to optimize system integration and performance. The ideal candidate has a strong background in NoC IP development and an educational background in Electrical or Computer Engineering. Competitive salary with bonuses available.

Qualifications

• Proven experience as a Cache Coherency Architect or Design Engineer focusing on NoC IP development.
• Strong understanding of cache hierarchies and their interaction with NoC interconnects.
• Experience in cache coherency verification and validation techniques.

Responsabilités

• Evaluate existing and industry-standard cache coherency protocols.
• Collaborate with SoC design teams for seamless integration.
• Analyze performance bottlenecks and power consumption.

Connaissances

Cache coherency protocols

SoC architecture

Analytical skills

Communication

Collaboration

Problem-solving

Formation

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field

Outils

HDLs

SoC design tools

Description du poste

A leading semiconductor solutions provider in Provence-Alpes-Côte d'Azur is seeking a Cache Coherency Architect to design high-performance cache coherency solutions. This role involves collaboration with hardware, software, and verification teams to optimize system integration and performance. The ideal candidate has a strong background in NoC IP development and an educational background in Electrical or Computer Engineering. Competitive salary with bonuses available.