Cache Coherency Architect - SoC & NoC / Architect Cache Cohenrency F/H

Arteris; Biot; Sur place; EUR 80 000 - 110 000; Plein temps

Résumé du poste

A leading semiconductor solutions provider in Provence-Alpes-Côte d'Azur is seeking a Cache Coherency Architect to design high-performance cache coherency solutions. This role involves collaboration with hardware, software, and verification teams to optimize system integration and performance. The ideal candidate has a strong background in NoC IP development and an educational background in Electrical or Computer Engineering. Competitive salary with bonuses available.

Qualifications

• Proven experience as a Cache Coherency Architect or Design Engineer focusing on NoC IP development.
• Strong understanding of cache hierarchies and their interaction with NoC interconnects.
• Experience in cache coherency verification and validation techniques.

Responsabilités

• Evaluate existing and industry-standard cache coherency protocols.
• Collaborate with SoC design teams for seamless integration.
• Analyze performance bottlenecks and power consumption.

Connaissances

Cache coherency protocols

SoC architecture

Analytical skills

Communication

Collaboration

Problem-solving

Formation

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field

Outils

HDLs

SoC design tools

Description du poste

Overview

Arteris is seeking a Cache Coherency Architect to define and optimize cache coherency solutions within Arteris' advanced NoC IP portfolio. You will collaborate with hardware designers, verification engineers, software developers, and other stakeholders to create high-performance, power-efficient, and reliable NoC IP solutions that enable seamless integration with other NoC interconnects and system IP.

Responsibilities

• Cache Coherency Architecture: Evaluate existing and industry-standard cache coherency protocols; maintain and improve the proprietary coherency protocol used within Arteris' configurable NoC IP; develop scalable cache coherency architectures aligned with SoC design goals; analyze customer requirements for cache-coherent system architectures, including partitioning large designs into chiplets using die-to-die and chip-to-chip architectures based on standards like CXL, UCIe, and PCIe; set performance goals (PPA) for configurable IP.
• NoC Integration: Collaborate with SoC design teams to ensure seamless integration of cache coherency into the SoC architecture; optimize Cache Coherency Architecture and uArchitecture within the NoC to minimize latency and improve bandwidth.
• Performance and Power Optimization: Analyze performance bottlenecks and power consumption; propose and implement innovative solutions to enhance overall efficiency; collaborate with hardware and software teams to verify and optimize cache coherency mechanisms.
• Protocol Verification: Support verification teams in developing verification strategies to ensure correctness and robustness of cache coherency protocols and NoC IP implementation; assist emulation teams in testing and debugging to validate cache coherency behaviors under various scenarios for functional correctness and performance.
• Cross-Functional Collaboration: Interact with marketing and sales to collect customer input and understand market and product requirements; collaborate with hardware design, software development, and system architecture teams to address needs and issues; provide technical support to the FAE team for product integration in customer designs.
• Industry Research and Innovation: Stay up-to-date with cache coherency and NoC technology advancements; evaluate emerging methodologies and standards, proposing their integration to enhance NoC IP offerings.
• Documentation and Communication: Prepare detailed technical documentation, including architecture specifications and design guidelines; effectively communicate complex technical concepts to technical and non-technical stakeholders.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
• Proven experience as a Cache Coherency Architect, Design Engineer, or similar role with a focus on NoC IP development.
• In-depth knowledge of SoC and NoC architecture, cache coherency protocols, and memory hierarchy.
• Strong understanding of cache hierarchies and their interaction with NoC interconnects.
• Experience in cache coherency verification and validation techniques.
• Familiarity with hardware description languages (HDLs) and SoC design tools.
• Strong analytical and problem-solving skills with a strategic mindset; excellent communication and collaboration abilities.
• Familiarity with HDLs and NoC IP development tools; prior experience in designing coherent systems is advantageous.

Compensation and About Arteris

Base Salary depending on qualification and experience between 80 to 110 KE per year, plus bonus.

Joining our team as a Cache Coherency Architect for our NoC IP development offers a unique opportunity to contribute to state-of-the-art semiconductor solutions. This is a highly visible role within the organization. If you are passionate about cache coherency and NoC IP design, we encourage you to apply and be part of our dynamic team.

About Arteris: Arteris is a leading provider of system IP for accelerating SoC development across today’s electronic systems. Arteris NoC interconnect IP and SoC integration automation technology enable higher performance with lower power and faster time to market.

With over 250 employees, headquarters in Silicon Valley, and offices worldwide, we support a wide range of customers from startups to technology leaders. Learn more at arteris.com.

Seniority level: Mid-Senior level

Employment type: Full-time

Job function: Information Technology

Industries: Semiconductor Manufacturing