Principal DV Engineer – SoC Interconnect & Memory

Arteris; Biot; On-site; EUR 110,000 - 140,000; Full time

Job summary

Arteris is seeking a Senior Staff / Principal Design Verification Engineer in Biot, France, to design and deliver interconnect and memory hierarchy solutions for leading SoCs. You will work with an expert team to verify RTL and system-level designs using UVM, Verilog, and advanced verification methodologies.

You will build test benches, integrate VIPs, develop automation tools, and drive regressions, metrics, and dashboarding, contributing to high-quality, configurable solutions across mobile,

Qualifications

• Proficient in RTL Verilog and UVM-based test benches.
• Experience with Python, Shell, and JavaScript scripting.
• Experience integrating vendor VIPs for unit and system verification.
• Familiarity with Arm AMBA protocols.
• Experience with high-performance, low-power designs.

Responsibilities

• UVM based test bench development and debugging
• Defining, documenting, developing, and executing RTL verification test/coverage at the system level
• Triaging Regressions, Debugging RTL designs in Verilog and System Verilog
• Help improve and refine the verification process, methodology, and metrics
• Develop, maintain, and test engineering design automation tools infrastructure to improve our frontend design and verification process.
• Monitor automated systems, isolate problems, and perform routine diagnostics checks & repairs.
• Run regressions, configure Jenkins builds, and record regression data
• Build/maintain regression dashboards & database to view trends and progress in numerical and graphical formats
• Evaluate existing automation infrastructure for areas of improvement
• Provide clear, concise documentation of the implementation/flow and usage of automation processes.

Skills

RTL Verilog

UVM

Test bench debugging

Python

Shell scripting

JavaScript

Vendor VIPs

AMBA protocols

Education

MS degree in EE/CS

BS degree minimum

Tools

Arm AMBA protocols

Job description

Arteris is seeking a Senior Staff / Principal Design Verification Engineer in Biot, France, to design and deliver interconnect and memory hierarchy solutions for leading SoCs. You will work with an expert team to verify RTL and system-level designs using UVM, Verilog, and advanced verification methodologies.

You will build test benches, integrate VIPs, develop automation tools, and drive regressions, metrics, and dashboarding, contributing to high-quality, configurable solutions across mobile,