Principal Design Verification Engineer

Arteris; Biot; On-site; EUR 110,000 - 140,000; Full time

Job summary

Arteris is seeking a Senior Staff / Principal Design Verification Engineer in Biot, France, to design and deliver interconnect and memory hierarchy solutions for leading SoCs. You will work with an expert team to verify RTL and system-level designs using UVM, Verilog, and advanced verification methodologies.

You will build test benches, integrate VIPs, develop automation tools, and drive regressions, metrics, and dashboarding, contributing to high-quality, configurable solutions across mobile,

Qualifications

• Proficient in RTL Verilog and UVM-based test benches.
• Experience with Python, Shell, and JavaScript scripting.
• Experience integrating vendor VIPs for unit and system verification.
• Familiarity with Arm AMBA protocols.
• Experience with high-performance, low-power designs.

Responsibilities

• UVM based test bench development and debugging
• Defining, documenting, developing, and executing RTL verification test/coverage at the system level
• Triaging Regressions, Debugging RTL designs in Verilog and System Verilog
• Help improve and refine the verification process, methodology, and metrics
• Develop, maintain, and test engineering design automation tools infrastructure to improve our frontend design and verification process.
• Monitor automated systems, isolate problems, and perform routine diagnostics checks & repairs.
• Run regressions, configure Jenkins builds, and record regression data
• Build/maintain regression dashboards & database to view trends and progress in numerical and graphical formats
• Evaluate existing automation infrastructure for areas of improvement
• Provide clear, concise documentation of the implementation/flow and usage of automation processes.

Skills

RTL Verilog

UVM

Test bench debugging

Python

Shell scripting

JavaScript

Vendor VIPs

AMBA protocols

Education

MS degree in EE/CS

BS degree minimum

Tools

Arm AMBA protocols

Job description

Description

Do you want to contribute to the backbone of some of the world's most popular SoCs? As a Senior Staff / Principal Design Verification Engineer at Arteris, you will work with an expert team to design and deliver interconnect & memory hierarchy solutions for some of the world's most sophisticated mobile, telecom, automotive, and consumer SoC designs. You will create designs in a powerful language that blends traditional RTL with leading-edge software to provide extremely configurable, testable, and high-quality solutions. You will go home at the end of the day, amazed at all the places where your creations end up. You will have the opportunity to be part of a proven, successful startup, and to influence the development environment, architecture, verification, and everything in-between - you will no longer be stuck in a silo or just a cog in the machine. Your co-workers will be an experienced team of industry experts who love what they do.

Key Responsibilities

• UVM based test bench development and debugging
• Defining, documenting, developing, and executing RTL verification test/coverage at the system level
• Triaging Regressions, Debugging RTL designs in Verilog and System Verilog
• Help improve and refine the verification process, methodology, and metrics
• Develop, maintain, and test engineering design automation tools infrastructure to improve our frontend design and verification process.
• Monitor automated systems, isolate problems, and perform routine diagnostics checks & repairs.
• Run regressions, configure Jenkins builds, and record regression data
• Build/maintain regression dashboards & database to view trends and progress in numerical and graphical formats
• Evaluate existing automation infrastructure for areas of improvement
• Provide clear, concise documentation of the implementation/flow and usage of automation processes.

Experience Requirements / Qualifications

• Verification flow enhancements using a scripting language such as Shell scripts, Python & JavaScript
• Strong RTL (Verilog) and UVM/C test bench debugging skills
• Experience integrating vendor-provided VIPs for unit and system-level verification
• Experience with Arm AMBA protocols
• This opportunity involves high-performance, low-power designs on a highly visible project

Education Requirements

• MS degree in EE, CS, or equivalent preferred. BS degree minimum.