Postdoc: AI/FPGA for GNSS Robustness

Institut Mines-Télécom; Plouzané; On-site; EUR 32,000 - 39,000; Full time

Benefits offered by this job

On-site cafeteria

Public transport subsidies

Generous leave package

Partial teleworking possible

Job summary

IMT Atlantique, a leading engineering school within the Institut Mines-Télécom, is seeking a Postdoctoral Researcher in the MEE department to develop FPGA-ready AI/DSP algorithms for robust GNSS receivers. The project STRIKEER partners with ARKANE and ArianeGroup to advance hardware-aware algorithms for drones and launchers.

You will optimize a real-time hybrid AI/DSP architecture on Zynq UltraScale+ devices, addressing SWaP constraints and delivering validated FPGA implementations.

Qualifications

• You have a PhD in digital electronics, embedded systems, or algorithm-architecture co-design.
• Experience in FPGA implementation of hybrid AI/DSP processing chains and GNSS/CRPA systems is essential.
• Strong autonomy, organizational skills, and ability to work in multidisciplinary teams.

Responsibilities

• Convert hybrid AI/DSP processing algorithms into FPGA-ready implementations.
• Integrate and optimize a real-time hybrid AI/DSP architecture on a Zynq UltraScale+ FPGA.
• Perform FPGA-In-the-Loop validation and on-target verification of the CRPA processing chain.
• Ensure documentation, traceability, and dissemination of results.

Skills

digital FPGA design

Verilog/VHDL

Fixed-point arithmetic

Quantized neural nets

GNSS/CRPA systems

Zynq UltraScale+

HLS

FPGA-In-the-Loop

Education

PhD in digital electronics, embedded systems, or algorithm-architecture co-design

Tools

Vivado

Vitis

AMD/Xilinx toolchains

High-Level Synthesis (HLS)

Brevitas

FINN

hls4ml

Job description

IMT Atlantique, a leading engineering school within the Institut Mines-Télécom, is seeking a Postdoctoral Researcher in the MEE department to develop FPGA-ready AI/DSP algorithms for robust GNSS receivers. The project STRIKEER partners with ARKANE and ArianeGroup to advance hardware-aware algorithms for drones and launchers.

You will optimize a real-time hybrid AI/DSP architecture on Zynq UltraScale+ devices, addressing SWaP constraints and delivering validated FPGA implementations.