PCIe/IP Verification Engineer (Hybrid, Sofia)

Rambus.com; Aix-en-Provence; Hybride; EUR 50 000 - 70 000; Plein temps

Avantages offerts par ce poste

Flexible work environment

Résumé du poste

Rambus.com is seeking a mid-level Design and Verification Engineer to join our team. The ideal candidate will engage in RTL design and verification for PCIe controller technologies and will work in a hybrid environment with three days onsite and two days remote. Candidates should have a bachelor’s or master’s degree in Electronics Engineering or Computer Science, with over six years of experience in verification using Verilog/SystemVerilog. Strong analytical and interpersonal skills are a must.

Qualifications

• 6+ years of experience in verification with Verilog and SystemVerilog.
• 6+ years of experience in complex ASIC/VLSI verification.
• 6+ years of experience with UVM and third-party VIP experience is a plus.

Responsabilités

• Integrate PCIe IP with vendor PHY module using Verilog RTL.
• Verify IP integration with a dedicated simulation environment.
• Develop and support test cases for verification environments.

Connaissances

Verilog RTL design

Problem-solving

Interpersonal skills

Python and shell scripting

Formation

Bachelor or Master’s degree in Electronics Engineering or Computer Science

Description du poste

Rambus.com is seeking a mid-level Design and Verification Engineer to join our team. The ideal candidate will engage in RTL design and verification for PCIe controller technologies and will work in a hybrid environment with three days onsite and two days remote. Candidates should have a bachelor’s or master’s degree in Electronics Engineering or Computer Science, with over six years of experience in verification using Verilog/SystemVerilog. Strong analytical and interpersonal skills are a must.