MTS Verification Engineering

Rambus.com; Aix-en-Provence; Sur place; EUR 50 000 - 70 000; Plein temps

Avantages offerts par ce poste

Flexible work environment

Résumé du poste

Rambus.com is seeking a mid-level Design and Verification Engineer to join our team. The ideal candidate will engage in RTL design and verification for PCIe controller technologies and will work in a hybrid environment with three days onsite and two days remote. Candidates should have a bachelor’s or master’s degree in Electronics Engineering or Computer Science, with over six years of experience in verification using Verilog/SystemVerilog. Strong analytical and interpersonal skills are a must.

Qualifications

• 6+ years of experience in verification with Verilog and SystemVerilog.
• 6+ years of experience in complex ASIC/VLSI verification.
• 6+ years of experience with UVM and third-party VIP experience is a plus.

Responsabilités

• Integrate PCIe IP with vendor PHY module using Verilog RTL.
• Verify IP integration with a dedicated simulation environment.
• Develop and support test cases for verification environments.

Connaissances

Verilog RTL design

Problem-solving

Interpersonal skills

Python and shell scripting

Formation

Bachelor or Master’s degree in Electronics Engineering or Computer Science

Description du poste

Overview

Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional mid‑level Design and Verification Engineer to join our PHY integration team in Sofia, Bulgaria. The successful candidate will participate in pre‑silicon RTL design and verification activities related to PCIe controller soft IP development and PHY integrations on leading‑edge PCI‑Express and CXL controller technologies. This is a full‑time position.

Rambus offers a flexible work environment, embracing a hybrid approach for the majority of our office‑based roles. We encourage employees to spend an average of at least three days per week working onsite while also allowing for two days of remote work if you are located in Sofia.

Responsibilities

• Verilog RTL design to integrate different IPs together such as PCIe IP with vendor PHY module
• Verify the IP integration with a dedicated simulation environment
• Develop and support test cases of different verification environments
• Support worldwide customers on the IP integration
• Get familiar with the existing verification process and propose improvements
• Maintain traceability from the customer or product specification to the architecture and verification results
• Track and maintain verification productivity metrics
• Report periodically on progress and difficulties

Qualifications

• "Can Do" attitude
• Bachelor or Master’s degree in Electronics Engineering, Computer Science, or related disciplines
• Strong analytical and problem‑solving skills
• Excellent interpersonal skills
• Open to traveling abroad
• Experience working in an international organization and with teams in France, USA, Taiwan, and India
• Because Rambus operates internationally, very good English is important for the position

Technical Experience

• 6+ years of experience in verification with Verilog, SystemVerilog, FPGA prototyping
• 6+ years of experience with complex ASIC/VLSI verification
• 6+ years of experience with UVM. Any third‑party VIP experience is a plus.
• 6+ years of experience in a multinational company
• Experience with creating documentation, Python, shell scripting, etc.

Rambus is proud to be an Equal Employment Opportunity and affirmative action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, or other applicable legally protected characteristics.

Rambus is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans during our job application procedures. If you require assistance or an accommodation due to a disability, please feel free to inform us in your application.