FPGA Hardware Design Internship: PQC Accelerators

Quantum Software; Paris; Hybride; EUR 10 000 - 15 000; Plein temps

Résumé du poste

CryptoNext Security seeks an FPGA Hardware Design Engineer intern to own a key PQC accelerator project on an embedded platform. You will develop RTL in SystemVerilog, integrate accelerators, and evaluate performance on the Zynq MPSoC board, focusing on NTT or Keccak functions for ML-KEM/ML-DSA within the CryptoNext Quantum Safe Library.

Required skills include FPGA RTL design, Vivado/Quartus experience, C under Linux, and strong codesign interest.

Qualifications

• Hands-on FPGA RTL design with SystemVerilog/Verilog or VHDL.
• Experience with FPGA toolchains (Vivado/Quartus) on dev boards.
• Strong C programming under Linux with basic assembly knowledge.
• Interest in hardware/software codesign and embedded systems.
• Git proficiency and standard software workflows.
• Shell scripting, Makefiles and compiler toolchains familiarity.
• Experience with profilers and debuggers for performance optimization.
• Ability to work independently and communicate results clearly.

Responsabilités

• Develop system-level RTL code using SystemVerilog.
• Integrate accelerators into a complete hardware/software system.
• Evaluate performance impact on the target embedded platform.
• Explore PQC hardware acceleration concepts (NTT or Keccak).
• Work on the AMD Xilinx ZCU104 / Zynq MPSoC target.

Connaissances

FPGA development

RTL design

Vivado/Quartus

C under Linux

Git workflows

Shell scripting

Profilers/Debuggers

Independent work

Formation

Final-year student / M2 / Master in a related field

Outils

QEMU

Verilator

Xilinx QEMU fork

Description du poste

CryptoNext Security seeks an FPGA Hardware Design Engineer intern to own a key PQC accelerator project on an embedded platform. You will develop RTL in SystemVerilog, integrate accelerators, and evaluate performance on the Zynq MPSoC board, focusing on NTT or Keccak functions for ML-KEM/ML-DSA within the CryptoNext Quantum Safe Library.

Required skills include FPGA RTL design, Vivado/Quartus experience, C under Linux, and strong codesign interest.