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CryptoNext Security is seeking an FPGA Hardware Design Engineer intern in Paris, France, to own a key project at the hardware/software codesign intersection for PQC accelerators. You will design RTL in SystemVerilog, integrate accelerators with software, and evaluate performance on an AMD Xilinx ZCU104/MPSoC platform.
The role focuses on NTT and Keccak state permutation implementations for ML-KEM/ML-DSA within the CryptoNext Quantum Safe Library, and requires hands-on work with FPGA tooling and
CryptoNext Security is seeking an FPGA Hardware Design Engineer intern in Paris, France, to own a key project at the hardware/software codesign intersection for PQC accelerators. You will design RTL in SystemVerilog, integrate accelerators with software, and evaluate performance on an AMD Xilinx ZCU104/MPSoC platform.
The role focuses on NTT and Keccak state permutation implementations for ML-KEM/ML-DSA within the CryptoNext Quantum Safe Library, and requires hands-on work with FPGA tooling and