Internship - FPGA Hardware Design - PQ Cryptography Hardware Accelerator

Quantum Software; Paris; Hybride; EUR 10 000 - 15 000; Plein temps

Résumé du poste

CryptoNext Security seeks an FPGA Hardware Design Engineer intern to own a key PQC accelerator project on an embedded platform. You will develop RTL in SystemVerilog, integrate accelerators, and evaluate performance on the Zynq MPSoC board, focusing on NTT or Keccak functions for ML-KEM/ML-DSA within the CryptoNext Quantum Safe Library.

Required skills include FPGA RTL design, Vivado/Quartus experience, C under Linux, and strong codesign interest.

Qualifications

• Hands-on FPGA RTL design with SystemVerilog/Verilog or VHDL.
• Experience with FPGA toolchains (Vivado/Quartus) on dev boards.
• Strong C programming under Linux with basic assembly knowledge.
• Interest in hardware/software codesign and embedded systems.
• Git proficiency and standard software workflows.
• Shell scripting, Makefiles and compiler toolchains familiarity.
• Experience with profilers and debuggers for performance optimization.
• Ability to work independently and communicate results clearly.

Responsabilités

• Develop system-level RTL code using SystemVerilog.
• Integrate accelerators into a complete hardware/software system.
• Evaluate performance impact on the target embedded platform.
• Explore PQC hardware acceleration concepts (NTT or Keccak).
• Work on the AMD Xilinx ZCU104 / Zynq MPSoC target.

Connaissances

FPGA development

RTL design

Vivado/Quartus

C under Linux

Git workflows

Shell scripting

Profilers/Debuggers

Independent work

Formation

Final-year student / M2 / Master in a related field

Outils

QEMU

Verilator

Xilinx QEMU fork

Description du poste

Who we are

CryptoNext Security is a deeptech startup specializing in post-quantum cryptography. Our solutions help businesses and institutions prepare for a future where quantum computers will challenge traditional data security. We work with leading clients in finance, defense, and telecommunications.

About the role

As part of an exploratory project on hardware accelerators for post-quantum cryptography (PQC), we are looking for a highly motivated FPGA Hardware Design Engineer to take ownership of a key strategic project at the intersection of hardware/software codesign (FPGA development and low-level C) and post-quantum cryptographic accelerators. You will work on the design, integration, and evaluation of hardware accelerators for well-identified mathematical functions used in post-quantum cryptographic algorithms, with a strong focus on demonstrating concrete performance benefits on a real embedded platform.

Your mission

You will study state-of-the-art approaches described in the scientific literature on PQC hardware acceleration, including relevant academic work such as this recent study, and implement the selected ones. You will focus in particular on the Number Theoretic Transform (NTT) and the Keccak state permutation function, two key computational functions involved in the implementation of algorithms such as ML-KEM and ML-DSA (lattice-based PQC algorithms).

You will be responsible for developing system-level RTL code using SystemVerilog, integrating the resulting accelerators into a complete hardware/software system, and evaluating their impact on application-level performance. The target platform will be an AMD Xilinx ZCU104 development board, equipped with a Zynq UltraScale+ MPSoC.

The primary objective of the internship is to demonstrate, on the target platform, that a hardware accelerator for either the NTT or the Keccak permutation can effectively accelerate the corresponding ML-KEM or ML-DSA implementation in the CryptoNext Quantum Safe Library (C-QSL).

Required skills

Must-have

• FPGA development, RTL design using Verilog, SystemVerilog or VHDL
• Experience with AMD Vivado or Intel Altera Quartus and FPGA development platforms
• Good programming skills in C under Linux, with basic knowledge of assembly language
• Strong interest in hardware/software codesign and embedded systems
• Experience with Git and standard software development workflows
• Familiarity with shell scripting, Makefiles, and compiler toolchains
• Experience using profilers and debuggers to analyze and optimize software performance
• Ability to work independently, investigate technical problems, and communicate results clearly

Nice-to-have

• Knowledge of AMBA protocols, such as AXI, AHB, APB, or CHI
• Experience with JTAG-based debugging
• Experience with QEMU, including the Xilinx fork of QEMU
• Experience with QEMU/SystemC/Verilator co-simulation
• Previous exposure to post-quantum cryptography, lattice-based cryptography, ML-KEM, ML-DSA, NTT or DFT, or Keccak (or more generally hash functions)
• Familiarity with embedded Linux and Zynq UltraScale+ MPSoC architectures

Internship details

• Duration: 6 months
• Period: December 2026 – June 2027
• Education: Final-year engineering student or M2 / Master's degree in computer engineering, electrical engineering, embedded systems, microelectronics, or a related field

QUANTUM ROLE CONTEXT | Appended by Quantum.Jobs v2

Role context:

Hardware engineering roles specializing in post-quantum cryptography exist to accelerate intensive mathematical computations by offloading algorithms to specialized silicon logic. Positioned between cryptographic algorithm researchers and system integration teams, this role bridges low-level hardware design with application software layers. Engineers in this domain design custom logic circuits to optimize throughput, reduce latency, and minimize resource consumption in embedded platforms. This function enables security implementations to meet real‑time operational constraints within legacy infrastructure and high‑throughput enterprise networks undergoing post‑quantum migration.

Quantum ecosystem relevance:

While not creating quantum computing hardware directly, post-quantum hardware engineering serves as critical enabling infrastructure for quantum-safe cybersecurity. As quantum processors threaten traditional public-key encryption standards, organizations require hardware‑accelerated defensive systems. This role strengthens the commercialization and deployment readiness of quantum-resistant security libraries across industries such as finance, defense, and telecommunications. By validating cryptographic accelerators on programmable logic devices, the role supports the practical ecosystem transition toward long‑term quantum resilience across critical software systems.

Capability signals:

- Hardware and software codesign for low-level embedded system integration

- Digital logic implementation for computationally intensive mathematical operations

- Optimization of cryptographic primitives on reconfigurable hardware platforms

- Performance benchmarking and verification of RTL code on target hardware

- Cross‑layer integration of custom hardware modules with system software libraries