FPGA Hardware Design Intern: Post-Quantum Accelerators

CryptoNext Security SAS; Paris; Sur place; EUR 12 000 - 18 000; Plein temps

Résumé du poste

CryptoNext Security SAS is seeking an FPGA Hardware Design Engineer for an internship focused on hardware accelerators for post-quantum cryptography. You will design, implement, and evaluate PQC accelerators on an embedded AMD Xilinx ZCU104 MPSoC platform within a HW/SW codesign context.

Key work includes RTL development in SystemVerilog, integrating accelerators, and assessing performance benefits for ML-KEM/ML-DSA on the CryptoNext Quantum Safe Library.

Qualifications

• Proficiency in FPGA RTL design using Verilog/SystemVerilog or VHDL.
• Strong C programming under Linux with basic assembly knowledge.
• Experience with Git and standard software workflows.
• Ability to work independently and communicate results clearly.
• Familiarity with shell scripting, Makefiles, and toolchains.

Responsabilités

• Develop system-level RTL code using SystemVerilog.
• Integrate accelerators into a complete hardware/software system.
• Evaluate impact on application-level performance on the target AMD Xilinx ZCU104 platform.

Connaissances

FPGA RTL design

Verilog/SystemVerilog

C under Linux

Git

Shell scripting

Makefiles

Profilers & debuggers

Independent work

Embedded systems

Formation

Final-year engineering student or M2/Master's in computer engineering, electrical engineering, embedded systems, microelectronics

Outils

AMD Vivado

Intel Quartus

FPGA development platforms

Description du poste

CryptoNext Security SAS is seeking an FPGA Hardware Design Engineer for an internship focused on hardware accelerators for post-quantum cryptography. You will design, implement, and evaluate PQC accelerators on an embedded AMD Xilinx ZCU104 MPSoC platform within a HW/SW codesign context.

Key work includes RTL development in SystemVerilog, integrating accelerators, and assessing performance benefits for ML-KEM/ML-DSA on the CryptoNext Quantum Safe Library.