FPGA Hardware Design Intern: PQC Accelerators (NTT/Keccak)

Cryptonext-Security; Paris; Sur place; EUR 12 000 - 17 000; Plein temps

Résumé du poste

CryptoNext Security in France is seeking an ambitious FPGA Hardware Design Engineer intern to drive a key project at the intersection of hardware/software codesign and PQC accelerators. You will design, integrate and evaluate RTL-based accelerators on an embedded platform.

The target is the Zynq UltraScale+ MPSoC on the AMD Xilinx ZCU104; you will work on NTT or Keccak functions, with a focus on practical performance gains for ML-KEM/ML-DSA within the CryptoNext Quantum Safe Library.

Qualifications

• Must have FPGA development experience and RTL design using Verilog/SystemVerilog/VHDL.
• Experience with AMD Vivado or Intel Quartus and FPGA development platforms.
• Strong C programming in Linux with basic knowledge of assembly language.
• Interest in hardware/software codesign and embedded systems.
• Experience with Git and standard software development workflows.
• Familiarity with shell scripting, Makefiles, and compiler toolchains.
• Experience using profilers and debuggers to analyze and optimize software performance.
• Ability to work independently, investigate technical problems, and communicate results clearly.

Responsabilités

• Study PQC hardware acceleration approaches described in literature.
• Implement selected approaches focusing on NTT and Keccak functions.
• Develop RTL in SystemVerilog and integrate accelerators into a complete system.
• Evaluate performance on the AMD ZCU104 development board.
• Demonstrate acceleration for ML‑KEM or ML‑DSA in the CryptoNext Quantum Safe Library (C-QSL).

Connaissances

FPGA development

RTL design (Verilog/SystemVerilog/VHDL

AMD Vivado

Intel Quartus

C under Linux

Assembly basics

Git

Shell scripting

Makefiles

Profilers & debuggers

Codesign & embedded systems

Communication of results

Formation

Final-year engineering student or Master’s degree

Outils

QEMU/SystemC/Verilator

QEMU (Xilinx fork)

Xilinx Vivado

Intel Quartus

Description du poste

CryptoNext Security in France is seeking an ambitious FPGA Hardware Design Engineer intern to drive a key project at the intersection of hardware/software codesign and PQC accelerators. You will design, integrate and evaluate RTL-based accelerators on an embedded platform.

The target is the Zynq UltraScale+ MPSoC on the AMD Xilinx ZCU104; you will work on NTT or Keccak functions, with a focus on practical performance gains for ML-KEM/ML-DSA within the CryptoNext Quantum Safe Library.