FPGA Hardware Design Intern — PQC Accelerators

CryptoNext Security; Paris; Sur place; EUR 12 000 - 18 000; Plein temps

Résumé du poste

CryptoNext Security is seeking an FPGA Hardware Design Engineer intern to lead hardware/software co-design efforts for PQC accelerators. You will implement RTL in SystemVerilog/Verilog, integrate accelerators on the Zynq MPSoC platform, and evaluate performance improvements on real embedded hardware.

The role targets ML‑KEM/ML‑DSA workflows, with a focus on NTT and Keccak blocks, on an AMD Xilinx ZCU104 board, contributing to the CryptoNext Quantum Safe Library.

Qualifications

• Experience in FPGA RTL design and verification.
• Proficiency with Verilog/SystemVerilog or VHDL.
• Familiarity with Linux-based development and build tools.

Responsabilités

• Develop RTL code for hardware accelerators in SystemVerilog.
• Integrate accelerators into a complete hardware/software system on the target board.
• Evaluate impact on application performance using real benchmarks and datasets.

Connaissances

FPGA RTL design

Verilog SystemVerilog VHDL

AMD Vivado / Intel Quartus

C under Linux

Git and workflows

Shell scripting

Profilers and debuggers

Independent problem solving

AMBA/AXI knowledge

JTAG debugging

QEMU/SystemC/Verilator

Embedded Linux / Zynq MPSoC

Formation

Final-year engineering student or M2 / Master's

Outils

QEMU

QEMU/Xilinx fork

Description du poste

CryptoNext Security is seeking an FPGA Hardware Design Engineer intern to lead hardware/software co-design efforts for PQC accelerators. You will implement RTL in SystemVerilog/Verilog, integrate accelerators on the Zynq MPSoC platform, and evaluate performance improvements on real embedded hardware.

The role targets ML‑KEM/ML‑DSA workflows, with a focus on NTT and Keccak blocks, on an AMD Xilinx ZCU104 board, contributing to the CryptoNext Quantum Safe Library.