SoC RTL Integration Lead — Tape-out Ready, 4d/wk

Semidynamics; Barcelona; Hybrid; EUR 90,000 - 130,000; Full time

Benefits offered by this job

4 days per week in Barcelona office

1 day work from home

Competitive package

Job summary

Semidynamics, a Barcelona-based semiconductor company, is seeking an SoC Top RTL Integration Engineer to weave CPU clusters, memory, accelerators and IP into the top-level RTL. You will manage interconnects (AXI, APB, CHI), define IOs and pads, and produce timing constraints with PD teams, driving toward tape-out.

This senior role requires hands-on experience integrating large SoCs, debugging lint, CDC, RDC issues, and scripting in Python and C to automate flows, collaborating with architecture,

Qualifications

• Degree in Electrical Engineering, Electronic Engineering, Computer Engineering or a related field.
• 8+ years of experience in digital/SoC design.
• Strong hands-on RTL design experience (SystemVerilog/Verilog).
• Proven experience integrating multiple subsystems on large SoCs.
• Experience connecting subsystems through interconnects and/or NoCs, with solid knowledge of AXI and APB.
• Proven track record on one or more tape-outs.
• Hands-on experience with lint, CDC and RDC checks.
• Experience writing and managing SDC constraints and integrating chip IOs.
• Working knowledge of Python and C for scripting and automation (user level).
• Fluent English, written and spoken.

Responsibilities

• Integrate multiple subsystems (CPU clusters, memory, accelerators, peripherals and third-party IP) into the SoC top-level RTL.
• Connect subsystems through interconnects and NoCs using AXI, APB, CHI.
• Define and integrate the chip's IOs, including connections to pads.
• Write and maintain SDC timing constraints for the integrated design, coordinating with PD teams.
• Run, debug and close lint, CDC and RDC checks at SoC top level.
• Integrate the top-level clock, reset and power infrastructure, and contribute to UPF power intent.
• Develop Python and C scripts to automate integration flows and support bring-up.
• Collaborate with architecture, verification, DFT and physical design teams to drive tape-out.

Skills

RTL design

SystemVerilog/Verilog

Python

C

Education

Electrical Engineering or related

Tools

lint

CDC

RDC

Job description

Semidynamics, a Barcelona-based semiconductor company, is seeking an SoC Top RTL Integration Engineer to weave CPU clusters, memory, accelerators and IP into the top-level RTL. You will manage interconnects (AXI, APB, CHI), define IOs and pads, and produce timing constraints with PD teams, driving toward tape-out.

This senior role requires hands-on experience integrating large SoCs, debugging lint, CDC, RDC issues, and scripting in Python and C to automate flows, collaborating with architecture,