SoC Top RTL Lead

Semidynamics; Barcelona; Hybrid; EUR 90,000 - 120,000; Full time

Benefits offered by this job

4 days per week in Barcelona office

1 day working from home

1 week of work from anywhere

Job summary

Semidynamics, a Barcelona-based semiconductor company, is seeking an SoC Top RTL Lead to own the top-level RTL of high-performance SoCs. You will drive the design from specification through tape-out, defining clock, reset and IO architectures, and guiding a team of engineers across architecture, verification and physical design.

This hands-on leadership role requires writing and reviewing RTL while mentoring engineers and coordinating cross-team efforts to deliver robust, scalable SoCs on

Qualifications

• Degree in Electrical/Electronic/Computer Engineering or related field.
• 8+ years of experience in digital/SoC design.
• Strong hands-on RTL design experience (SystemVerilog/Verilog).
• Proven experience leading SoC top-level RTL integration on large, high-performance SoCs.
• Proven tape-out experience on high-performance SoCs.
• Strong background in SoC clock and reset architecture.
• Experience with signal distribution, including delay propagation and signal integrity.
• Hands-on experience defining and managing interfaces with pads and IOs.
• Solid understanding of ESD protection concepts.
• Experience as a technical lead, guiding and mentoring engineers.
• Fluent English, written and spoken.

Responsibilities

• Own the SoC top-level RTL and lead the integration of CPU clusters, subsystems and third-party IP into the SoC top.
• Lead and mentor a team of RTL engineers: plan, prioritise and review their work, and set design standards and best practices.
• Define and implement the SoC reset architecture, including reset domains, sequencing and synchronisation.
• Define and implement the SoC clock architecture, including clock topologies, clock generation and distribution across the chip.
• Design the power infrastructure for multiple power domains, including isolation strategies and power-on sequencing.
• Plan signal distribution across the SoC, addressing delay propagation and signal integrity.
• Define and manage the chip's interfaces with the external world: pads, IOs and low-level technology cells such as tri-state buffers, including ESD protection considerations.
• Own lint, CDC and RDC closure at SoC top level and drive the definition of UPF power intent.
• Act as the technical interface with architecture, verification, DFT and physical design teams, driving the SoC through to tape-out.

Skills

SystemVerilog/Verilog

RTL design

SoC top-level RTL integration

Team leadership

Clock and reset architecture

Signal integrity

Pads/IO interfaces

Tape-out experience

Lint/CDC/RDC closure

Education

Degree in Electrical/Electronic/Computer Engineering or related field

Tools

UPF-based design tools

Job description

Semidynamics is a Barcelona-based semiconductor company, founded in 2016, that designs European processor technology built on the open RISC-V standard. We develop fully customisable 64-bit RISC-V processor IP, including out-of-order and in-order CPU cores and dedicated vector and tensor units, for demanding AI, machine learning and high-performance computing workloads.

Our team combines deep architecture expertise with hands-on silicon experience, and we are growing to deliver complete, high-performance SoC solutions to our customers.

Role overview

We are looking for an SoC Top RTL Lead to own the top-level RTL of our high-performance SoCs. You will lead the integration of all subsystems into the SoC top, define the clock, reset, power and IO architecture, and drive the design from specification through to tape-out.

This is a hands-on technical leadership role. You will write and review RTL yourself while guiding a team of engineers, and act as the main point of contact for top-level design across architecture, verification and physical design.

Key Responsibilities

• Own the SoC top-level RTL and lead the integration of CPU clusters, subsystems and third-party IP into the SoC top.
• Lead and mentor a team of RTL engineers: plan, prioritise and review their work, and set design standards and best practices.
• Define and implement the SoC reset architecture, including reset domains, sequencing and synchronisation.
• Define and implement the SoC clock architecture, including clock topologies, clock generation and distribution across the chip.
• Design the power infrastructure for multiple power domains, including isolation strategies and power-on sequencing.
• Plan signal distribution across the SoC, addressing delay propagation and signal integrity.
• Define and manage the chip's interfaces with the external world: pads, IOs and low-level technology cells such as tri-state buffers, including ESD protection considerations.
• Own lint, CDC and RDC closure at SoC top level and drive the definition of UPF power intent.
• Act as the technical interface with architecture, verification, DFT and physical design teams, driving the SoC through to tape-out.

Required qualifications

• Degree in Electrical Engineering, Electronic Engineering, Computer Engineering or a related field.
• 8+ years of experience in digital/SoC design.
• Strong hands-on RTL design experience (SystemVerilog/Verilog).
• Proven experience leading SoC top-level RTL integration on large, high-performance SoCs.
• Proven track record on one or more tape-outs of high-performance SoCs.
• Strong background in SoC clock and reset architecture.
• Experience with signal distribution, including delay propagation and signal integrity.
• Hands-on experience defining and managing interfaces with the external world, including low-level technology cells such as pads and tri-state buffers.
• Solid understanding of ESD protection concepts.
• Experience as a technical lead, guiding and mentoring engineers and coordinating work across teams.
• Fluent English, written and spoken.

Nice to have

• Experience with power distribution and management across multiple power domains, including isolation and power-on sequencing.
• Hands-on experience with UPF-based low-power design flows.
• Experience running and signing off lint, CDC and RDC checks on large SoC designs.

Why Semidynamics

• Work at one of Europe's most promising deep-tech semiconductor scale-ups
• Accelerated development path, with room to grow into confidential computing, memory isolation and software security
• 4 days per week in the Barcelona office (city center), 1 day working from home
• 1 week of work from anywhere in the world
• Competitive package
• A collaborative, technical, growth-oriented environment that values direct ownership and clear thinking