Senior SoC RTL Integration Engineer

Hireroo

Barcelona

Hybrid

EUR 90,000 - 120,000

Full time

2 days ago

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Benefits offered by this job

Flexible working hours

Hybrid model: 4 days in office, 1 day‑

Relocation bonus

Housing search support

Visa support

Private medical insurance

Language classes

Virtual shares

Monthly food allowance

25 days annual leave

Job summary

Hireroo Ltd in Barcelona is seeking a Senior SoC RTL Integration Engineer to unify processor clusters, memory, accelerators and peripherals into a complete chip design. You will own RTL integration at the SoC top level and ensure timing, clocks, resets and interfaces are ready for implementation.

The role requires 8+ years in digital/SoC design, Verilog/SystemVerilog RTL expertise, and tapeout experience. Hybrid work: 4 days in office, 1 day from home; salary is competitive with relocation and

Qualifications

8+ years in digital or SoC design.
Strong Verilog/SystemVerilog RTL design experience.
Integration of multiple subsystems within large SoCs.
Experience with interconnects or NoCs (AXI / APB).
Participation in at least one completed tapeout.
Experience with lint, CDC and RDC checks.
SDC constraints and chip IO integration.
Fluent English.
Engineering degree.

Responsibilities

Integrate CPU clusters, memory, accelerators, peripherals and external IP into the SoC.
Connect subsystems through interconnects and NoCs using AXI, APB and CHI.
Integrate chip IOs and pad connections.
Create and maintain SDC timing constraints with physical design teams.
Run, debug and close lint, CDC and RDC checks.
Integrate clocks, resets and power infrastructure, contributing to UPF power intent.
Develop Python and C scripts and tests for automation and initial hardware testing.
Resolve integration issues across engineering teams and support delivery through tapeout.

Skills

Verilog/SystemVerilog

RTL integration

NoCs / interconnects

Python scripting

C scripting

Tapeout experience

Lint / CDC / RDC checks

SDC constraints

Engineering degree

Fluent English

8+ years experience

Education

Engineering degree

Job description

Specialization: Semiconductor Design and SoC Integration

Job Description

Our partner is looking for a Senior SoC RTL Integration Engineer to bring processor clusters, memory, accelerators and peripherals together into a complete chip design.

You will own RTL integration at the SoC top level, ensuring that subsystems communicate correctly and that timing constraints, clocks, resets and interfaces are ready for implementation.

The role involves close collaboration with architecture, verification, DFT and physical design teams, taking integrated designs through checks, issue resolution and tapeout.

Location: Barcelona, Spain
Working model: Hybrid, 4 days in the office, 1 day from home
Employment: Full time

Responsibilities

Integrate CPU clusters, memory, accelerators, peripherals and external IP into the SoC.
Connect subsystems through interconnects and NoCs, using AXI, APB and, where applicable, CHI.
Integrate chip IOs and pad connections.
Create and maintain SDC timing constraints with physical design teams.
Run, debug and close lint, CDC and RDC checks.
Integrate clocks, resets and power infrastructure, contributing to UPF power intent.
Develop Python and C scripts and tests for automation and initial hardware testing.
Resolve integration issues across engineering teams and support delivery through tapeout.

Mandatory Requirements

8+ years in digital or SoC design.
Strong practical Verilog/SystemVerilog RTL design experience.
Proven integration of multiple subsystems within large SoCs.
Experience with interconnects or NoCs, including AXI and APB.
Participation in at least one completed tapeout.
Practical experience with lint, CDC and RDC checks.
Experience managing SDC constraints and chip IO integration.
Working knowledge of Python and C for scripting and automation.
Relevant engineering degree.
Fluent English.

Important: Candidates must demonstrate direct SoC RTL integration experience through tapeout. Verification experience alone does not meet this requirement.

Optional / Desired