Senior SoC Physical Design Lead – RTL-to-GDSII & Signoff

Analog Devices, Inc.; Madrid; On-site; EUR 120,000 - 180,000; Full time

Job summary

Analog Devices, Inc. in Madrid, Spain is seeking a Principal Physical Design Engineer to own end-to-end RTL-to-GDSII implementation and signoff for complex SoCs.

You will drive timing closure, select Cadence/Synopsys PD flows, and lead a distributed PD team across locations to meet project milestones. The role requires 10+ years of PD experience and a strong background in floorplanning, CTS, routing, DRC/LVS, and power analysis.

Qualifications

• 10+ years of physical design experience with tape-outs on advanced technology nodes.
• B.Tech./M.Tech. or higher in Electrical or Electronics Engineering or equivalent.

Responsibilities

• Own RTL-to-GDSII implementation, including floorplanning, CTS, routing, and STA closure.
• Review timing constraints and provide feedback on timing closure to PD and Design teams.
• Hands-on experience with Cadence and Synopsys PD flows to drive implementation and signoff.
• Lead setup and hold timing closure, IR/EM analysis, congestion resolution, and PPAs.
• Lead signoff activities, including multi-mode multi-corner STA, DRC/LVS, and power analysis.
• Provide leadership for a geographically distributed PD team across locations and manage priorities.
• Identify, evaluate, and mitigate technical risks and communicate trade-offs to stakeholders.

Skills

Physical design

Education

Electrical or Electronics Engineering

Tools

Cadence

Synopsys

Job description

Analog Devices, Inc. in Madrid, Spain is seeking a Principal Physical Design Engineer to own end-to-end RTL-to-GDSII implementation and signoff for complex SoCs.

You will drive timing closure, select Cadence/Synopsys PD flows, and lead a distributed PD team across locations to meet project milestones. The role requires 10+ years of PD experience and a strong background in floorplanning, CTS, routing, DRC/LVS, and power analysis.