Senior Analog Layout & Automation Engineer (IP Reuse)

Analog Devices; Madrid; On-site; EUR 90,000 - 120,000; Full time

Job summary

Analog Devices, Inc. in Madrid, Spain, seeks a Senior Layout & Design Automation Engineer to lead complex analog/mixed-signal layouts from floorplanning through tapeout and to drive automation that improves productivity across IPs and subsystems.

You will own layout for critical IP, collaborate with circuit designers, and mentor junior engineers while ensuring reliability, ESD, and manufacturability across multiple process nodes. This role demands strong scripting and cross-group collaboration.

Qualifications

• 8+ years of analog or mixed-signal IC layout experience.
• Proven experience delivering silicon in advanced and mature process technologies.
• Deep knowledge of device matching, parasitic effects, shielding and isolation techniques, reliability and ESD considerations.
• Scripting and automation experience using one or more of: SKILL, Python, Shell/Bash, Tcl.

Responsibilities

• Lead development of complex analog and mixed-signal layouts from floorplanning through tapeout.
• Own layout execution for critical IP, subsystems, and test-chip developments.
• Drive high-quality layout implementation for data converters, power management circuits, amplifiers, PLLs and clock-generation circuits.
• Drive successful DRC, LVS, ERC and extraction closure; ensure manufacturability.

Skills

Analog IC layout

Mixed-signal layout

Cadence Virtuoso

Layout XL / VXL

Calibre DRC/LVS/ERC

Parasitic extraction

Scripting (Python, Tcl, Shell)

Automation development

Device matching

AI-assisted workflows

Education

BS/MS in Electrical/Electronics Engineering

Tools

Cadence Virtuoso

Layout XL / VXL

Calibre DRC/LVS/ERC

Parasitic extraction

Python

SKILL

Shell/Bash

Tcl

Job description

Analog Devices, Inc. in Madrid, Spain, seeks a Senior Layout & Design Automation Engineer to lead complex analog/mixed-signal layouts from floorplanning through tapeout and to drive automation that improves productivity across IPs and subsystems.

You will own layout for critical IP, collaborate with circuit designers, and mentor junior engineers while ensuring reliability, ESD, and manufacturability across multiple process nodes. This role demands strong scripting and cross-group collaboration.