Senior Formal Verification Lead - RTL/Power Convergence

Semidynamics; Cataluña; Presencial; EUR 70.000 - 90.000; Jornada completa

Descripción de la vacante

Semidynamics is seeking a static formal verification lead to ensure functional correctness and low-power intent across the design lifecycle. You will drive RTL-to-Gate and Gate-to-Gate equivalence checks, debug LEC failures, and guarantee convergence across synthesis, place-and-route, and ECO cycles.

You will collaborate with RTL, Synthesis, DFT, and Physical Design teams to resolve design mismatches, perform ECO validation, and develop automation for LEC sign-off.

Formación

• Bachelor's or Master’s degree in Electrical/Electronics Engineering or related discipline.
• 7+ years of experience in Formal Verification/LEC.
• Strong expertise in tools like Synopsys Formality/VC LP.
• Understanding of low-power design concepts (UPF).
• Experience with synthesis, netlist optimizations, and equivalence debugging.
• Proficiency in scripting languages such as TCL, Python, or Perl.

Responsabilidades

• Perform RTL-to-Gate and Gate-to-Gate equivalence checks using tools like Synopsys Formality.
• Debug LEC failures, including clock gating, retention, isolation, and level shifters.
• Ensure convergence of LEC across synthesis, place-and-route, and ECO cycles.
• Work closely with RTL, Synthesis, DFT, and Physical Design teams to resolve design mismatches.
• Handle ECO validation and ensure equivalence closure post-design changes.
• Develop automation scripts and improve methodology for LEC sign-off.

Conocimientos

Formal Verification

LEC

Synopsys Formality

VC LP

UPF

RTL-Gate checks

TCL/Python

Hierarchical LEC

Educación

Bachelors/Masters in EE/ECE

Herramientas

Synopsys Formality

VC LP

Descripción del empleo

Semidynamics is seeking a static formal verification lead to ensure functional correctness and low-power intent across the design lifecycle. You will drive RTL-to-Gate and Gate-to-Gate equivalence checks, debug LEC failures, and guarantee convergence across synthesis, place-and-route, and ECO cycles.

You will collaborate with RTL, Synthesis, DFT, and Physical Design teams to resolve design mismatches, perform ECO validation, and develop automation for LEC sign-off.