Senior Physical Design Engineer - RTL-to-GDSII & Signoff

Analog Devices; Valencia; Presencial; EUR 90.000 - 130.000; Jornada completa

Descripción de la vacante

Analog Devices, Inc. in Valencia seeks a Principal Physical Design Engineer to drive end-to-end RTL-to-GDSII implementation for complex SoCs, coordinating with Design, DFT, Verification and CAD teams to deliver high‑quality silicon.

You will lead timing closure, signoff, and multi-site PD delivery, mentor a distributed team, manage risks, and ensure on-time milestones and robust PPA on advanced nodes.

Formación

• B.Tech., M.Tech., or higher qualification in Electrical or Electronics Engineering.
• 10+ years of physical design experience with successful tape-outs on advanced technology nodes.
• Hands-on experience with industry-standard physical design and signoff tools.

Responsabilidades

• Own RTL-to-GDSII implementation, including floorplanning, CTS, routing, equivalence checking, ECO implementation, and STA closure.
• Review implementation results with SDC timing constraints and provide feedback to PD and Design teams.
• Drive Cadence and/or Synopsys based physical design flows to implement, optimize, and signoff.
• Lead timing closure, IR/EM analysis, congestion resolution, and power analysis to meet PPC targets.
• Lead signoff activities across multi-mode multi-corner STA and DRC/LVS checks.
• Provide leadership for a geographically distributed Physical Design team and coordinate with locations.
• Identify and mitigate technical risks and communicate trade-offs to stakeholders.

Educación

B.Tech., M.Tech., or higher in Electrical or Electronics Engineering

Descripción del empleo

Analog Devices, Inc. in Valencia seeks a Principal Physical Design Engineer to drive end-to-end RTL-to-GDSII implementation for complex SoCs, coordinating with Design, DFT, Verification and CAD teams to deliver high‑quality silicon.

You will lead timing closure, signoff, and multi-site PD delivery, mentor a distributed team, manage risks, and ensure on-time milestones and robust PPA on advanced nodes.