Senior ASIC Verification Lead - UVM Validation & Growth

Bull; Madrid; On-site; EUR 90,000 - 120,000; Full time

Benefits offered by this job

Flexible work schedule

Learning and growth opportunities

Job summary

Bull is seeking an Asic Verification Lead to join its dynamic team in Madrid or Barcelona. You will drive verification strategy for Bull’s high-end servers, leading UVM-based methodologies and collaborating with architecture and design teams to ensure reliability and performance.

The ideal candidate has 8+ years of ASIC/SoC verification experience, a BE/BTech or ME/MTech, and deep knowledge of UVM, SystemVerilog, and C++.

Qualifications

• 8+ years of ASIC/SoC verification experience required.
• Deep knowledge of UVM/SystemVerilog and coverage-driven verification.
• Experience leading verification strategy and teams.

Responsibilities

• Acquire knowledge of ASIC architecture and microarchitecture.
• Define verification strategy and environments; publish specs.
• Write and execute test plans with design team.
• Develop coverage models and verification environments using UVM-SystemVerilog/C++.
• Analyze and debug simulation results; improve coverage to meet targets.
• Propose tool/methodology improvements to boost productivity.
• Mentor junior engineers to write maintainable, reusable code.

Skills

ASIC verification leadership

UVM, SystemVerilog

C++

SoC/ASIC verification

Mentoring juniors

Education

Bachelor’s degree (BE/BTech) or Master’s degree (ME/MTech)

Tools

UVM

C++ tooling

Job description

Bull is seeking an Asic Verification Lead to join its dynamic team in Madrid or Barcelona. You will drive verification strategy for Bull’s high-end servers, leading UVM-based methodologies and collaborating with architecture and design teams to ensure reliability and performance.

The ideal candidate has 8+ years of ASIC/SoC verification experience, a BE/BTech or ME/MTech, and deep knowledge of UVM, SystemVerilog, and C++.