ASIC Verification Engineer

Bull; Madrid; Presencial; EUR 42.000 - 60.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Flexible work schedule

Learning and growth opportunities

Descripción de la vacante

Bull is seeking an ASIC Verification Engineer in Madrid or Barcelona to join our high-performance computing and AI-focused teams. You will contribute to constraint-random, coverage-driven verification of complex ASICs, using UVM and SystemVerilog, with C++ for test environments.

You will collaborate with architecture and design teams, define verification strategies, develop test plans, and drive coverage to meet targets on time.

Formación

• Experience with constraint-random, coverage-driven verification for complex ASICs or SoCs.
• Proficiency in UVM verification methodologies and SystemVerilog testbenches.
• Hands-on with simulation and coverage analysis tools; able to define test plans and environments.

Responsabilidades

• Acquire architecture and microarchitecture knowledge of the ASIC from specs and design teams.
• Define verification strategies, environments, and required simulation setups.
• Develop, maintain verification specs; create test plans with the design team.
• Build verification environments, test cases, and coverage models using UVM/SystemVerilog/C++.
• Track, debug, and fix simulation errors; analyze coverage and improve tests.
• Suggest tools and methodologies to boost verification productivity.

Conocimientos

Constraint-random verification

Coverage-driven verification

UVM

SystemVerilog

C++

Educación

BE/BTech or ME/MTech

Herramientas

Simulation tools

Coverage analysis tools

Descripción del empleo

Date: Oct 20, 2026

Ref. No: 548147

Location: Madrid, ES

Bull is a story. One with a century of European innovation and a working environment where experts design powerful, sustainable, and sovereign digital solutions, enabling states and industries to retain full control over their data and their AI.

Bull is also thousands of engineers, researchers and passionate tech people shaping the future of high‑performance computing, AI, and quantum technologies.

Every day, our teams push the boundaries of what is technologically possible – from next‑generation HPC architectures to exascale supercomputers – supported by world‑class R&D, more than 1,600 patents, and unique end‑to‑end capabilities spanning hardware design, software engineering, data science and quantum research.

We are a people‑centric, innovation‑driven company, where collaboration spans Europe, the Americas and India. We share a common vision of a responsible and sustainable innovation that delivers concrete impact for our customers.

We are looking for an ASIC Verification Engineer to join Bull’s innovative team.

The role involves contributing to the verification of a complex ASIC using constraint-random, coverage-driven functional verification methodologies, based on the UVM verification standard, as part of the development of ASICs such as network controllers, routers, and cache coherence controllers for high-end, high-performance Bull servers, including big data and exascale systems.

Responsibilities

• Acquire knowledge of the architecture and microarchitecture of the ASIC by studying specifications and interacting with the architecture and logical design teams.
• Participate in defining overall verification strategies and methodologies, as well as the required simulation environments.
• Develop, maintain, and publish verification specifications. Define test plans in close collaboration with the logical design team.
• Develop verification environments, test cases, and coverage models using UVM / SystemVerilog / C++.
• Track, analyze, and debug simulation errors.
• Monitor and analyze simulation coverage results and improve tests accordingly to achieve coverage targets on time.
• Submit recommendations on tools and methodologies to improve productivity.

What We're Looking For

Experience & Education

• Experience: 3–5 years
• Education: Bachelor’s Degree (BE / BTech) or Master’s Degree (ME / MTech)

Competences & Skills

• Experience using constraint-random, coverage-driven functional verification methodologies under the UVM verification framework to ensure full and effective verification of complex ASICs.
• Mastery of UVM or equivalent verification methodologies.
• Profound knowledge of simulation and coverage analysis tools.
• Strong problem-solving skills, with the ability to quickly identify root causes and implement fixes or workarounds.
• Participation in the successful verification of a complex SoC or ASIC.

Personal Skills

• Strong interpersonal skills with excellent verbal and written communication.
• Ability to work collaboratively within a team and interact closely with design and architecture engineers.
• Language agility: Ability to work professionally in English and Spanish, including meetings, documentation, and workshops.

Location

• Madrid or Barcelona. Candidates from other locations in Spain may also be considered.

Benefits

• Flexible Work Schedule; Half day Fridays and an intensive summer workday supporting work life balance.
• Learning and Growth Opportunities to work with advanced AI technologies in an innovative and supportive R&D environment.

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