Senior Power Integrity Engineer - AI Accelerator PDN Lead

Semidynamics; Barcelona; Hybrid; EUR 90,000 - 130,000; Full time

Job summary

Semidynamics in Barcelona seeks a Senior IC Power Integrity engineer to own the PDN from regulator output to die bump, addressing impedance, IR drop, and decoupling across die, package, and board.

You will perform DC IR, AC impedance, transient analyses, and drive decoupling strategies while collaborating with CPM and silicon teams. The role is hybrid with 4 days in Barcelona and 1 day remote.

Qualifications

• 8+ years in power integrity for high-speed digital systems.
• Hands-on with PDN extraction and simulation tools (Ansys SIwave/HFSS, Cadence Sigrity/Clarity).
• Experience with DC IR, target impedance, transient droop and decap optimization on high-current rails.
• Reading a package substrate stackup and plane/via/cavity behavior.
• Python scripting for automation and post-processing.

Responsibilities

• Build and close DC IR, electro-thermal, AC impedance and transient PDN analysis from VR output through package to die bump.
• Set target impedance per rail and hold the design to it.
• Work with CPM and workload current profiles to size on-die, package and board decoupling, and to predict droop across all three droop timescales.
• Identify package–board anti-resonance and drive plane, via and decap changes that mitigate it.
• Translate PDN noise into jitter through PHY supply sensitivity, and feed the result back into the channel budget.
• Drive CPM and model requirements with IP, PHY and package vendors. Correlate against PDN impedance measurement and on-die droop telemetry, and support bring-up and power debug.

Skills

Power integrity for high-speed digital

PDN design

Electro-thermal analysis

DC IR

Transient droop

Python scripting

Tools

Ansys SIwave/HFSS

Cadence Sigrity/Clarity

Job description

Semidynamics in Barcelona seeks a Senior IC Power Integrity engineer to own the PDN from regulator output to die bump, addressing impedance, IR drop, and decoupling across die, package, and board.

You will perform DC IR, AC impedance, transient analyses, and drive decoupling strategies while collaborating with CPM and silicon teams. The role is hybrid with 4 days in Barcelona and 1 day remote.