PICs@ICFO Strategic Initiative: Postdoctoral Researcher in TGV Metallization and Seed-Layer Processes

Institute of Photonic Sciences; Castelldefels; On-site; EUR 42,000 - 54,000; Full time

Job summary

ICFO invites applications for a postdoctoral researcher position within the PICs@ICFO Strategic Initiative focused on Through-Glass Vias metallization and seed-layer processes. The successful candidate will develop and optimize seed layers and deposition methods for high-aspect-ratio vias in glass to enable copper interconnects.

The role emphasizes hands-on thin-film deposition, surface activation, adhesion promotion, and integration with subsequent plating steps, in collaboration with the

Qualifications

• Hands-on experience in thin-film deposition and metallization for semiconductor/packaging contexts.
• Experience with high-aspect-ratio Through-Glass Vias and seed layers.
• Familiarity with surface cleaning, activation, and adhesion-promotion processes.
• Knowledge of seed-layer stacks (e.g., Ti/Cu, Cr/Cu, TiW/Cu) and interconnect integration.
• Ability to optimize multiple deposition methods (sputtering, evaporation, ALD/CVD).

Responsibilities

• Develop and optimize seed-layer deposition processes for high-aspect-ratio Through-Glass Vias
• Develop substrate cleaning, glass-surface activation, and adhesion-promotion processes
• Develop adhesion, barrier, and conductive seed stacks such as Ti/Cu, Cr/Cu, TiW/Cu
• Optimize sputtering, evaporation, electroless, ALD or CVD-assisted, and hybrid deposition approaches
• Achieve continuous and conformal seed coverage along via entrances, sidewalls, and exits
• Characterize thickness, morphology, resistivity, adhesion, continuity, and wafer-level uniformity
• Identify and mitigate shadowing, seed discontinuity, oxidation, delamination, and cracking
• Coordinate with the laser and glass team to align via geometry and surface condition with seeding, plating, and interconnection requirements

Skills

Thin-film deposition

Seed-layer deposition

Surface activation

Metallization

Sputtering

ALD/CVD

Characterization

Tools

Sputtering systems

Evaporation

Electroless plating

ALD

CVD

Job description

PICs@ICFO Strategic Initiative: Postdoctoral Researcher in TGV Metallization and Seed-Layer Processes

As part of the PICs@ICFO Strategic Initiative, ICFO coordinates PIXEurope, a flagship Pilot Line funded under the European Chips JU program, focused on Advanced Photonic Integrated Circuits (PICs) through which ICFO is advancing frontier technologies, including optical interposers for Co-packaged optics for next-generation optoelectronic and photonic devices.

To strengthen this initiative, ICFO is seeking a highly motivated Engineer/Scientist with strong expertise in thin-film deposition and metallization of high-aspect-ratio Through-Glass Vias (TGVs).

Position Overview:,

We offer a post-doctoral position to a scientist with hands-on experience in thin-film deposition, surface preparation, and metallization for semiconductor, MEMS, or advanced-packaging applications. The successful candidate will develop, optimize, and scale reliable adhesion, barrier, and conductive seed layers inside high-aspect-ratio glass vias, ensuring continuity and compatibility with subsequent copper plating and interconnection processes.

Key Responsibilities:,

The selected candidate will be expected to:

• Develop and optimize seed-layer deposition processes for high-aspect-ratio Through-Glass Vias
  
• Develop substrate cleaning, glass-surface activation, and adhesion-promotion processes
  
• Develop adhesion, barrier, and conductive seed stacks such as Ti/Cu, Cr/Cu, TiW/Cu, and related systems
  
• Optimize sputtering, evaporation, electroless, ALD or CVD-assisted, and hybrid deposition approaches
  
• Achieve continuous and conformal seed coverage along via entrances, sidewalls, and exits
  
• Characterize thickness, morphology, resistivity, adhesion, continuity, and wafer-level uniformity
  
• Identify and mitigate shadowing, seed discontinuity, oxidation, delamination, and cracking
  
• Coordinate with the laser and glass team to align via geometry and surface condition with seeding, plating, and interconnection requirements
  

This position will report to the Prof. Dr. Valerio Pruneri, Director of the European Chips JU Pilot Line PIXEurope.

PIXEurope is co-funded by the Chips Joint Undertaking and national funding authorities of the Participating States, Spain, Ireland, The Netherlands, Finland, Belgium, Portugal, Poland, Austria, France, Italy, United Kingdom. In particular, it is co-funded by Spain through the Ministry for Digital Transformation and Civil Service under reference CJU-010000-2025-0005, as part of the Recovery, Transformation and Resilience Plan (PRTR).