Digital Verification Eng. - DDR/LPDDR IF Protocols

Hireroo

Barcelona

Hybrid

EUR 65,000 - 90,000

Full time

5 days ago

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Benefits offered by this job

Flexible hours

Hybrid work model

Relocation bonus

Housing search support

Visa support

Private medical insurance

Language classes

Virtual shares

Job summary

Hireroo Ltd. in Barcelona, Spain is seeking a Digital Verification Engineer to perform functional verification of DDR/LPDDR memory interfaces within complex ASIC/SoC designs.

You will develop and maintain SystemVerilog/UVM testbenches, debug protocol issues and drive coverage closure, ensuring functional correctness. This is a technical execution role requiring independent problem solving and ownership of verification tasks in collaboration with RTL, architecture and firmware teams.

Qualifications

5+ years in ASIC/SoC functional verification required.
DDR/LPDDR high-speed protocol verification experience essential.
AMBA protocols knowledge including AXI, AHB, CHI or CXS.
Strong SystemVerilog, UVM and coverage closure experience.
Experience with simulation tools like VCS/Xcelium/Questa.

Responsibilities

Perform functional verification of DDR/LPDDR interfaces at IP and subsystem levels.
Develop and maintain SystemVerilog/UVM testbenches.
Verify DDR/LPDDR and AMBA protocol compliance.
Debug RTL, verification model and specification mismatches.
Execute regressions, investigate failures and drive bug closure.
Contribute to functional coverage and verification signoff.
Optimize simulation performance and automate verification workflows.
Collaborate with RTL, architecture and firmware teams.
Maintain verification documentation and methodologies.

Skills

ASIC/SoC functional verification

DDR/LPDDR protocol verification

AMBA protocols (AXI/AHB/CHI/CXS)

SystemVerilog/UVM/coverage closure

VCS/Xcelium/Questa

RTL debugging

Independent problem solving

Engineering degree

Education

Engineering degree

Tools

VCS

Xcelium

Questa

Job description

Specialization: Semiconductor Design and Functional Verification

Job Description

Our partner is looking for a Digital Verification Engineer to perform functional verification of DDR/LPDDR memory interfaces within complex ASIC and SoC designs.

You will develop and maintain SystemVerilog/UVM testbenches, debug protocol issues and drive coverage closure, ensuring functional correctness and compliance.

This is a technical execution role requiring independent problem solving, ownership of verification tasks and collaboration with RTL, architecture and firmware teams.

Location: Barcelona, Spain

Working model: Hybrid, 4 days in the office, 1 day from home

Employment: Full time

Responsibilities

Perform functional verification of DDR/LPDDR interfaces at IP and subsystem levels.
Develop and maintain SystemVerilog/UVM testbenches.
Verify DDR/LPDDR and AMBA protocol compliance.
Debug RTL, verification model and specification mismatches.
Execute regressions, investigate failures and drive bug closure.
Contribute to functional coverage and verification signoff.
Optimize simulation performance and automate verification workflows.
Collaborate with RTL, architecture and firmware teams.
Maintain verification documentation and methodologies.

Mandatory Requirements

5+ years in ASIC/SoC functional verification.
Recent DDR/LPDDR or comparable high speed protocol verification experience.
Knowledge of AMBA protocols, including AXI, AHB, CHI or CXS.
Strong SystemVerilog, UVM and coverage closure experience.
Experience with VCS, Xcelium or Questa.
Good RTL debugging and SoC architecture knowledge.
Independent problem solving and verification task ownership.
Relevant engineering degree.

Important: Direct ASIC/SoC functional verification experience, including UVM development, protocol verification and coverage closure, is essential. RTL design, FPGA development or physical verification alone is insufficient.

Optional / Desired