FPGA Design Engineer — AI-Powered Space Payloads

Aistech Space; Barcelona; Hybrid; EUR 60.000 - 100.000; Vollzeit

Benefits dieser Stelle

Flexible hours

Hybrid work

On-site gym

Paddle courts

Daily fruit & coffee

International environment

23 vacation days + holidays

Zusammenfassung

Aistech Space in Barcelona seeks an expert FPGA Design Engineer to lead next‑gen image acquisition payloads. You’ll architect the digital brain, transforming raw high‑speed sensor data into actionable insights using VHDL and hardware acceleration.

You will manage data flow from FPGA pins to AI engines, integrate DMA streams, and ensure timing closure. Join a cross‑functional, agile team and contribute to documentation and blogs.

Qualifikationen

• BSc/MSc in Electronics, Telecommunications, or similar.
• Deep understanding of VHDL with Xilinx RTL optimization.
• Proficiency in Vivado/Vitis/Petalinux toolchain.
• Experience with Xilinx IP Integrator and AXI4 protocols.
• High-speed SerDes calibration and PCB constraints knowledge.
• DMA/Scatter-Gather DMA for high-bandwidth data.
• Experience with UVVM/OSVVM/UVM and self-checking testbenches.
• XSIM/ModelSim/Questa with Xilinx VIP experience.
• Scripting: Tcl for Vivado, Python for data analysis.
• Fluent in English.

Aufgaben

• Lead FPGA image acquisition and processing payload development.
• Architect the digital brain, transforming high-speed sensor data to insights.
• Manage data lifecycle from FPGA pins to AI engines and memory DMA.
• Work in agile, client-driven development iterations.
• Follow internal standards for project mgmt, documentation, and time management.
• Write articles for Aistech News and company blog.
• Develop company procedures and specification manuals.
• Suggest ideas to improve products and processes.

Kenntnisse

VHDL Expert

Vivado/Vitis

IP Integration

High-Speed Hardware

DMA/Data Transfer

Verification Skills

Simulation Tools

Scripting (Tcl/Python)

English Fluent

Ausbildung

BSc/MSc in Electronics/Telecommunications

Tools

Vivado Design Suite

Vitis Unified Software Platform

Petalinux

Jobbeschreibung

Aistech Space in Barcelona seeks an expert FPGA Design Engineer to lead next‑gen image acquisition payloads. You’ll architect the digital brain, transforming raw high‑speed sensor data into actionable insights using VHDL and hardware acceleration.

You will manage data flow from FPGA pins to AI engines, integrate DMA streams, and ensure timing closure. Join a cross‑functional, agile team and contribute to documentation and blogs.