FPGA Designer Engineer

Aistech Space; Barcelona; Híbrido; EUR 60.000 - 100.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Flexible hours

Hybrid work

On-site gym

Paddle courts

Daily fruit & coffee

International environment

23 vacation days + holidays

Descripción de la vacante

Aistech Space in Barcelona seeks an expert FPGA Design Engineer to lead next‑gen image acquisition payloads. You’ll architect the digital brain, transforming raw high‑speed sensor data into actionable insights using VHDL and hardware acceleration.

You will manage data flow from FPGA pins to AI engines, integrate DMA streams, and ensure timing closure. Join a cross‑functional, agile team and contribute to documentation and blogs.

Formación

• BSc/MSc in Electronics, Telecommunications, or similar.
• Deep understanding of VHDL with Xilinx RTL optimization.
• Proficiency in Vivado/Vitis/Petalinux toolchain.
• Experience with Xilinx IP Integrator and AXI4 protocols.
• High-speed SerDes calibration and PCB constraints knowledge.
• DMA/Scatter-Gather DMA for high-bandwidth data.
• Experience with UVVM/OSVVM/UVM and self-checking testbenches.
• XSIM/ModelSim/Questa with Xilinx VIP experience.
• Scripting: Tcl for Vivado, Python for data analysis.
• Fluent in English.

Responsabilidades

• Lead FPGA image acquisition and processing payload development.
• Architect the digital brain, transforming high-speed sensor data to insights.
• Manage data lifecycle from FPGA pins to AI engines and memory DMA.
• Work in agile, client-driven development iterations.
• Follow internal standards for project mgmt, documentation, and time management.
• Write articles for Aistech News and company blog.
• Develop company procedures and specification manuals.
• Suggest ideas to improve products and processes.

Conocimientos

VHDL Expert

Vivado/Vitis

IP Integration

High-Speed Hardware

DMA/Data Transfer

Verification Skills

Simulation Tools

Scripting (Tcl/Python)

English Fluent

Educación

BSc/MSc in Electronics/Telecommunications

Herramientas

Vivado Design Suite

Vitis Unified Software Platform

Petalinux

Descripción del empleo

Company Description:

Aistech Space is focused on generating affordable, recurrent, high-resolution thermal imagery of the planet to provide a new perspective of Earth’s changing resources. The company is based in Barcelona and aims to revolutionize remote sensing for environmental monitoring and resource management.

What you will do:

Aistech Space is seeking an expert FPGA Design Engineer to lead the development of our next-generation image acquisition and processing payloads. You will be the architect of the “digital brain” of our systems, transforming raw high-speed sensor data into actionable insights using cutting-edge VHDL logic and hardware acceleration.

This role is not just about writing code; it is about managing the entire data lifecycle—from the physical high-speed pins of the FPGA to the integration of AI engines and DMA streaming to memory. You will work at the intersection of hardware and high-level software, ensuring our systems are fast, synchronized, and reliable in demanding environments

In this role, you are expected to work as a team, functioning as an agile, highly collaborative unit focused on short, client-driven development iterations.

You will also be responsible for following internal standards and good practices in terms of project management, documentation, and time management, adopting an agile approach in your daily work.

The key objectives to be achieved in this position are:

• Understand Aistech Space mission objectives.
• Xilinx RTL Development: Design and optimize modular VHDL code for Xilinx 7-Series, UltraScale+, and Versal Adaptive SoCs.
• High-Speed I/O & Connectivity: Implement and debug high-speed transceivers (GTH/GTY) for protocols such as MIPI CSI-2, PCIe Gen3/4, and 10G/25G Ethernet.
• Advanced Data Path: Architect low-latency data movement using AXI4-Stream, AXI SmartConnect, and Xilinx Video DMA (VDMA) or DataMover IPs.
• AI Engine Integration: Deploy and optimize neural networks using the Vitis AI flow, integrating DPU (Deep Learning Processor Unit) cores into the FPGA fabric.
• Memory Management: Configure and optimize hardened DDR4/LPDDR4 memory controllers to handle multi-stream 4K/8K video buffering.
• Timing Closure: Author complex XDC constraints, manage multiple clock domains using MMCM/PLLs, and achieve timing closure on high-utilization designs.
• Verification & Debug: Perform hardware-in-the-loop debugging using Vivado ILA (Integrated Logic Analyzer) and Vitis Analyzer.
• Write articles regarding different areas of interest to be published in our Aistech News magazine and on our website blog.
• Actively engage in the development of documentation to build out the company procedures and specification manuals.
• Follow your curiosity to suggest new ideas to make our products and processes better.

Who you are:

Must:

• Degree: BSc/MSc in Electronics, Telecommunications, or similar.
• VHDL Expert: Deep understanding of Xilinx-specific RTL optimization (utilizing DSP48 slices, Block RAM, and UltraRAM efficiently).
• AMD Toolchain Expert: Proficiency in Vivado Design Suite, Vitis Unified Software Platform, and Petalinux.
• IP Integration: Extensive experience with Xilinx IP Integrator and the AXI4 protocol family (Memory Mapped, Stream, and Lite).
• High-Speed Hardware: Experience with SerDes calibration, eye-diagram analysis, and high-speed PCB constraints.
• DMA/Data Transfer: Proven experience implementing Scatter-Gather DMA for high-bandwidth sensor data.
• Verification Skills: Experience with advanced simulation environments (UVVM, OSVVM, or UVM) and self-checking testbenches.
• Simulation: Experience with Xilinx Simulator (XSIM) or third-party tools like ModelSim/Questa using Xilinx Verification IP (VIP).
• Scripting: Proficiency in Tcl for Vivado automation and Python for data analysis.
• Fluent in English.

Nice to have:

• Versal Experience: Knowledge of Versal AI Engines (AIE) and the Programmable Network on Chip (NoC).
• HLS Knowledge: Familiarity with Vitis HLS (C/C++ to RTL synthesis) for rapid IP development.
• Space/High-Reliability Experience: Familiarity with SEU (Single Event Upset) mitigation techniques and radiation-hardened design philosophies.

What You’ll Gain by Joining Us

• Be part of a passionate, collaborative, and respectful team.
• Enjoy a stable, permanent contract with a fast-growing company.
• Flexible working hours and hybrid work: 6 days/month from home.
• Competitive salary and flexible retribution through Cobee.
• Free access to paddle tennis courts and an on-site gym.
• Daily fresh fruit and coffee to keep you energized.
• Work in an international, diverse environment.
• 23 vacation days, plus Birthday, December 24 & 31 off.

To be considered for this position, you must already have the legal right to work in the European Union. We are unable to provide visa sponsorship.