FPGA Design Engineer for Space & Defense

Arquimea; Casares; Vor Ort; EUR 55.000 - 75.000; Vollzeit

Zusammenfassung

ARQUIMEA seeks an FPGA Design Engineer to craft and verify digital hardware for FPGAs, ASICs and SoCs for space and defense programs. You will define architectures, implement RTL, and lead verification from requirements to sign-off in a multinational team based in Madrid.

The candidate should have 5+ years in FPGA/digital hardware, HDL/VHDL/Verilog experience, and proficiency with Vivado and verification tools. English required; Spanish is a plus. Travel to EU/US may be required.

Qualifikationen

• Bachelor-level degree in Electrical/Electronic Engineering or related field.
• Master’s/PhD is valued for advanced roles.
• Solid academic background in digital circuit design and FPGA-based systems.
• At least 5 years of professional experience in digital hardware/FPGA design, preferably in high-reliability sectors.
• Proficient in English (written and spoken); Spanish a plus.

Aufgaben

• Develop FPGA IP cores, ASICs, and standard ICs for space and defense programs.
• Define architecture of digital ICs, SoCs, and FPGA IPs with trade-off analyses.
• Front-end RTL design and verification from requirements to sign-off.
• Model and simulate full solutions to optimize digital circuits.
• Plan, execute, and document FPGA verification, testing and debugging.
• Collaborate with validation and test teams during bring-up and qualification of IP blocks.

Kenntnisse

HDL front-end design

FPGA design tools

Digital design principles

SoC architecture knowledge

Verification activities

Testbench development

Git version control

Space/defense domain experience

Ausbildung

Electrical/Electronic Engineering

Master’s/PhD valued

Tools

Xilinx Vivado

HDL Author

ModelSim

Questa

Git

ECSS/MIL-STD knowledge

Jobbeschreibung

ARQUIMEA seeks an FPGA Design Engineer to craft and verify digital hardware for FPGAs, ASICs and SoCs for space and defense programs. You will define architectures, implement RTL, and lead verification from requirements to sign-off in a multinational team based in Madrid.

The candidate should have 5+ years in FPGA/digital hardware, HDL/VHDL/Verilog experience, and proficiency with Vivado and verification tools. English required; Spanish is a plus. Travel to EU/US may be required.