FPGA Verification & Validation Engineer

Aistech Space; Barcelona; Híbrido; EUR 70.000 - 100.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

On-site gym

Paddle tennis courts

Fresh fruit and coffee

Hybrid work

23 vacation days

Descripción de la vacante

Aistech Space in Barcelona seeks an expert FPGA Verification & Validation Engineer to define and execute the verification strategy for next-gen image payloads. You’ll ensure 100% reliability, timing compliance, and flawless performance before flight. Work in agile teams, building scalable testbenches and HIL frameworks.

Key objectives include advanced verification frameworks, Xilinx VIP usage, and robust AI engine/memory validation. Hybrid work with strong documentation culture is offered.

Formación

• Proven experience in advanced FPGA verification methodologies (UVVM, OSVVM, or UVM).
• Strong AMD/Xilinx toolchain proficiency (Vivado, Vitis, and simulators).
• Fluency in Python for automation and Tcl for workflow scripting.
• Solid knowledge of AXI4 protocol family and verification patterns.
• Excellent English communication for global collaboration.

Responsabilidades

• Architect and implement self-checking testbenches and verification environments.
• Lead hardware-in-the-loop (HIL) and flight-model verification campaigns.
• Verify high-speed I/O (GTH/GTY), MIPI CSI-2, PCIe Gen3/4, 10G/25G Ethernet.
• Validate data paths with AXI4-Stream and related IPs (VDMA, DataMover).
• Develop automation scripts in Tcl/Python for testing and results analysis.
• Document validation plans, test reports, and manuals.

Conocimientos

UVVM/OSVVM/UVM

Python scripting

Tcl scripting

AXI4 protocol

Xilinx Vivado/Vitis

VHDL verification

Agile teamwork

English communication

Educación

BSc/MSc Electronics

BSc/MSc Telecommunications

BSc/MSc Computer Science

Herramientas

Vivado

Vitis

ModelSim

QuestaSim

XSIM

Xilinx VIP

Descripción del empleo

Company Description:

Aistech Space is focused on generating affordable, recurrent, high-resolution thermal imagery of the planet to provide a new perspective of Earth’s changing resources. The company is based in Barcelona and aims to revolutionize remote sensing for environmental monitoring and resource management.

What you will do:

Aistech Space is seeking an expert FPGA Verification & Validation Engineer to build, lead, and execute the verification strategy for our next-generation image acquisition and processing payloads. Instead of designing the logic fabric, your primary mission will be to ensure the absolute reliability, timing compliance, and functional flawless performance of the “digital brain” of our systems before flight deployments.

You will architect and build advanced simulation frameworks and hardware-in-the-loop (HIL) testing infrastructures from scratch. Acting as the ultimate quality gatekeeper, you will test and push VHDL logic, AI engine integrations, and high-speed data paths to their limits, ensuring our satellite payloads operate with 100% predictability in the harsh environment of space.

In this role, you are expected to work as a team, functioning as an agile, highly collaborative unit focused on short, client-driven development iterations, while enforcing internal standards and good practices in project management, documentation, and time management.

The key objectives to be achieved in this position are:

• Understand Mission Objectives: Align FPGA validation protocols deeply with overall Aistech Space mission objectives.
• Advanced Verification Frameworks: Design and implement self-checking testbenches and advanced simulation environments utilizing UVVM, OSVVM, or UVM to comprehensively verify complex VHDL designs.
• Toolchain & Simulation Mastery: Run exhaustive functional and timing simulations using Xilinx Simulator (XSIM) or third-party tools like ModelSim/Questa, leveraging Xilinx Verification IP (VIP).
• High-Speed I/O & Connectivity Testing: Test, characterize, and debug high-speed transceivers (GTH/GTY) and critical interfaces like MIPI CSI-2, PCIe Gen3/4, and 10G/25G Ethernet.
• Data Path Validation: Formally verify low-latency data movement pipelines involving AXI4-Stream, AXI SmartConnect, and Xilinx Video DMA (VDMA) or DataMover IPs.
• Hardware-in-the-Loop (HIL) Debugging: Lead bench-level and flight-model hardware verification campaigns using Vivado ILA (Integrated Logic Analyzer), Vitis Analyzer, and standard laboratory equipment (oscilloscopes, logic analyzers).
• Timing Closure Verification: Critically review complex XDC constraints, analyze multi-clock domains managed by MMCM/PLLs, and validate timing margins on high-utilization designs.
• AI Engine & Memory Validation: Verify the robust deployment of neural networks through Vitis AI flow and validate hardened DDR4/LPDDR4 memory controllers under multi-stream 4K/8K video loads.
• Automation Strategy: Drive verification efficiency by developing automated testing script suites in Tcl for Vivado and Python for data/test results analysis.
• Documentation & Reporting: Actively engage in the development of comprehensive validation plans, test reports, and specification manuals to build out company procedures, and author technical articles for Aistech News or the company blog.

Who you are:

Must:

• Degree: BSc/MSc in Electronics, Telecommunications, Computer Science, or similar.
• Verification Expertise: Proven professional experience in advanced FPGA verification methodologies (UVVM, OSVVM, or UVM) and building modular, scalable testbenches.
• AMD Toolchain Proficiency: Solid experience within the AMD/Xilinx eco-system, including Vivado Design Suite, Vitis Unified Software Platform, and associated simulation environments.
• Protocol Familiarity: Strong working knowledge of the AXI4 protocol family (Memory Mapped, Stream, and Lite) and structural design verification patterns.
• Scripting Power: Fluency in Python for test automation and scripting, as well as Tcl for tool workflow automation.
• Fluent in English: Excellent communication skills for global, multidisciplinary collaboration.

Nice to have:

• Versal & HLS Exposure: Familiarity with validating Versal AI Engines (AIE), Programmable Network on Chip (NoC), or testing Vitis HLS generated blocks.
• High-Reliability Industry Experience: Prior exposure to NewSpace, aerospace, or defense industries, including knowledge of Single Event Upset (SEU) mitigation and radiation-hardened testing philosophies.
• Hardware Bring-up: Basic experience with SerDes calibration and eye-diagram analysis.

What You’ll Gain by Joining Us

• Be part of a passionate, collaborative, and respectful team.
• Enjoy a stable, permanent contract with a fast-growing company.
• Flexible working hours and hybrid work: 5 days/month from home.
• Competitive salary and flexible retribution through Cobee.
• Free access to paddle tennis courts and an on-site gym.
• Daily fresh fruit and coffee to keep you energized.
• Work in an international, diverse environment.
• 23 vacation days, plus Birthday, December 24 & 31 off.

To be considered for this position, you must already have the legal right to work in the European Union. We are unable to provide visa sponsorship.