ASIC Verification Lead

Atos SE; Madrid; Híbrido; EUR 70.000 - 90.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Flexible Work Schedule: Half day Fridays

Learning opportunities with advanced AI technologies

Intensive summer workday for work-life balance

Descripción de la vacante

Atos SE is seeking an Asic Verification Lead to verify complex ASIC architectures for high-end and exascale servers. The role involves driving verification strategy and collaborating closely with design teams for reliable semiconductor designs.

Applicants should have over 8 years of experience in ASIC verification, a Bachelor's or Master's degree, and be proficient in UVM methodologies. The position offers flexible work options, including remote work within Spain.

Formación

• 8+ years of experience in ASIC verification.
• Experience in the verification of complex ASICs or SoCs.
• Proficient in UVM or equivalent verification methods.

Responsabilidades

• Drive verification strategy and methodologies.
• Develop coverage models and verification environments using UVM-SystemVerilog / C++.
• Mentor junior engineers on maintainable and reusable code.

Conocimientos

Integrating ASIC functional verification team

Constraint-Random, Coverage-Driven verification methodologies

Mastering UVM or equivalent verification methodology

Educación

Bachelor's Degree (BE / BTech) or Master's Degree (ME / MTech)

Descripción del empleo

Asic Verification Lead

In this role, you will play a key part in verifying complex ASIC architectures used in Bull’s high‑end and exascale servers. You will drive verification strategy, lead UVM‑based methodologies, and work closely with architecture and design teams to ensure the reliability and performance of advanced semiconductor designs.

Responsibilities

• Acquire knowledge of the architecture and microarchitecture of the ASIC by studying specifications and interacting with the architecture and logical design teams.
• Participate in defining overall verification strategies and methodologies, and the required simulation environments. Develop, maintain and publish verification specifications.
• Write and perform closely test plans with the logical design team.
• Develop coverage models and verification environments using UVM-SystemVerilog / C++.
• Monitor, analyze and debug simulation errors.
• Monitor and analyze simulation coverage results to improve tests accordingly thereby achieving coverage targets on time.
• Submit recommendations on tools and methodologies to develop to improve productivity.
• Mentor junior engineers on how to produce a maintainable and reusable code across projects.

What we’re looking for

Education

• Experience: 8+ years
• Education: Bachelor's Degree (BE / BTech) or Master's Degree (ME / MTech)

Competences & Skills

• Integrating ASIC functional verification team.
• ASIC developed include network controller, router and cache coherence controller targeting Bull high-end servers and Bull high-performance ("big data" and "exascale") servers.
• Using "Constraint‑Random, Coverage‑Driven" functional verification methodologies underlying UVM verification framework to ensure full and effective verification of complex ASIC.
• Participated in the successful verification of a complex SoC or ASIC.
• Mastering UVM or equivalent verification methodology.

Location

• Madrid or Barcelona (or remote within Spain)
• Flexible Work Schedule: Half day Fridays and an intensive summer workday supporting work life balance.
• Learning and Growth: Opportunities to work with advanced AI technologies in an innovative and supportive R&D environment.