Senior ASIC Verification Engineer - Remote/Spain, Flex Hours

Atos; Madrid; Presencial; EUR 45.000 - 65.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Flexible Work Hours

Learning & Growth

Descripción de la vacante

Bull is seeking an experienced ASIC Verification Engineer to join our team in Madrid or remotely within Spain. The role focuses on constraint-random, coverage-driven verification of complex ASICs such as network controllers and routers, using UVM, SystemVerilog and C++.

You will collaborate with architecture and design teams to define strategies, develop test plans and verification environments. Ideal candidates have 3–5 years of experience and a Bachelor’s or Master’s degree in a relevant

Formación

• Experience using constraint-random, coverage-driven verification methodologies under the UVM verification framework.
• Mastery of UVM or equivalent verification methodologies.
• Proficient with simulation and coverage analysis tools.
• Strong problem-solving skills and ability to quickly identify root causes.
• Experience in verification of a complex SoC or ASIC.

Responsabilidades

• Acquire knowledge of ASIC architecture and microarchitecture by studying specs and interacting with design teams.
• Define overall verification strategies and environments; specify required simulation environments.
• Develop, maintain and publish verification specifications; define test plans with design team.
• Develop verification environments, test cases and coverage models using UVM/SystemVerilog/C++.
• Track, analyze and debug simulation errors.
• Monitor coverage results and improve tests to meet targets on time.
• Submit recommendations on tools and methods to boost productivity.

Conocimientos

UVM

SystemVerilog

C++

Constraint Random

Coverage Driven

ASIC verification

Debugging

Problem Solving

Educación

Bachelor's Degree

Master's Degree

Herramientas

Simulation Tools

Descripción del empleo

Bull is seeking an experienced ASIC Verification Engineer to join our team in Madrid or remotely within Spain. The role focuses on constraint-random, coverage-driven verification of complex ASICs such as network controllers and routers, using UVM, SystemVerilog and C++.

You will collaborate with architecture and design teams to define strategies, develop test plans and verification environments. Ideal candidates have 3–5 years of experience and a Bachelor’s or Master’s degree in a relevant