Digital Verification Intern: UVM & SystemVerilog

Monolithic Power Systems, Inc.; Barcelona; Presencial; EUR 18.000 - 26.000; Jornada completa

Descripción de la vacante

Monolithic Power Systems, Inc. in Barcelona, Spain invites a Digital Verification Engineer Intern to validate, simulate, and verify digital and mixed-signal ICs using ASIC tools.

You will interact with Senior Digital and Analog Engineers to develop system-level and behavioral models, write tests, and automate verification tasks. Requirements include a Bachelor’s or Master’s in Electrical Engineering with emphasis in Digital Design or VLSI, knowledge of SystemVerilog/UVM, and scripting abilities

Formación

• Degree in Electrical Engineering or related field; emphasis in digital design.
• Required familiarity with ASIC development processes and digital design techniques.
• Strong written and verbal communication; teamwork.
• Knowledge of DV languages (SystemVerilog, UVM) and RTL coding.

Responsabilidades

• Assist in creating Digital Verification environments with UVM and SystemVerilog.
• Write digital and mixed-signal test cases and assertions/checkers.
• Analyze and debug test results, coverage, and functional coverage.
• Support Verification IPs, tests, environments, and checkers.
• Assist with Test Plan generation from design requirements and datasheets.
• Collaborate with Senior Digital/Analog Engineers to model systems.
• Automate tasks and scripting; Gate-Level verification.

Conocimientos

SystemVerilog

UVM

RTL coding

Digital Design

Teamwork

Educación

Bachelor's or Master's in Electrical Engineering

Herramientas

Python

TCL

C/C++

Descripción del empleo

Monolithic Power Systems, Inc. in Barcelona, Spain invites a Digital Verification Engineer Intern to validate, simulate, and verify digital and mixed-signal ICs using ASIC tools.

You will interact with Senior Digital and Analog Engineers to develop system-level and behavioral models, write tests, and automate verification tasks. Requirements include a Bachelor’s or Master’s in Electrical Engineering with emphasis in Digital Design or VLSI, knowledge of SystemVerilog/UVM, and scripting abilities