Senior Design Verification Engineer

Beagle; Barcelona; Presencial; EUR 70.000 - 90.000; Jornada completa

Descripción de la vacante

Beagle is seeking a Senior Verification Engineer in Barcelona, Spain, to lead advanced verification of complex RTL designs. You will build testbenches, run simulations, and apply formal and dynamic verification methods.

You will work with design teams to ensure production-ready microprocessor architectures are correct and robust. The role requires 8+ years in digital design verification, strong SystemVerilog and UVM skills, scripting (Python/Perl/Bash/Tcl), and proficiency in English.

Formación

• Master’s or PhD in Computer Science, Electrical Engineering, or a related field.
• Proficiency in SystemVerilog and UVM.
• Strong scripting skills (Python, Perl, Bash, Tcl).
• 8+ years of relevant industry experience.
• Hands-on experience with simulation tools and regression management.
• Familiarity with revision control tools (git, svn).
• Proven experience in block-level, subsystem, and top-level verification.
• Background in both formal and dynamic verification methodologies.
• Excellent problem-solving skills and attention to detail.
• Strong communication and teamwork abilities.
• Proficiency in English (C1 level).

Responsabilidades

• Verify RTL designs at block, subsystem and top level to ensure correctness and functionality.
• Develop testbenches and run simulations to validate complex microprocessor architectures.
• Apply advanced verification methodologies to improve coverage and bug detection.
• Collaborate closely with design teams to deliver production-ready designs.
• Contribute to regression management and issue tracking.

Conocimientos

SystemVerilog

UVM

Python

Perl

Bash

Tcl

English (C1)

Problem solving

Teamwork

Educación

Master’s or PhD in Computer Science, Electrical Engineering, or a related field

Herramientas

Git

SVN

Descripción del empleo

ROLE: Senior Verification Engineer

LOCATION: Barcelona, Spain

SALARY: Negotiable

DURATION: Permanent

Description:

We are seeking an experienced Senior Verification Engineer with 8+ years of industry expertise in

digital design verification. The ideal candidate will have a strong background in SystemVerilog and

UVM, with proven experience in block-level, subsystem, and top-level verification. Knowledge of

both formal and dynamic verification methodologies is essential.

In this role, you will work within the Verification Team to ensure the correctness and

functionality of complex microprocessor architectures at the RTL level. You will develop and apply

advanced verification methodologies, build testbenches, run simulations, and collaborate closely

with design teams to deliver high-quality, production-ready designs.

Requirements:

• Master’s or PhD in Computer Science, Electrical Engineering, or a related field


• Proficiency in SystemVerilog and UVM


• Strong scripting skills (Python, Perl, Bash, Tcl)


• 8+ years of relevant industry experience


• Hands‑on experience with simulation tools and regression management


• Familiarity with revision control tools (git, svn)


• Proven experience in block-level, subsystem, and top-level verification


• Background in both formal and dynamic verification methodologies


• Excellent problem-solving skills and attention to detail


• Strong communication and teamwork abilities


• Proficiency in English (C1 level)