Senior/Principal DFT Engineer

Racyics; Frankfurt; Vor Ort; EUR 70.000 - 110.000; Vollzeit

Benefits dieser Stelle

Flexible working hours

Mobile work

Childcare contributions

Great team events

Zusammenfassung

Racyics is seeking an experienced DFT Engineer to extend our international team in Germany. The role involves developing DFT specifications, implementing full-chip and block-level test structures, and driving test pattern generation and coverage improvements.

You will collaborate with SoC and Physical Design teams to enhance testability, and work with test engineers to bring up patterns on silicon and debug yield issues. Prior DFT tool experience is required.

Qualifikationen

• Bachelor's/Master's Degree in Electrical Engineering, Information Technology or similar.
• At least 3+ years experience as DFT engineer.
• Strong knowledge of state-of-the-art DFT techniques and concepts like Scan test incl. Compression, On-chip clock controllers, IEEE 1500 core wrapping, LBIST.
• Deep experience with industry standard DFT tools from Synopsys, Mentor or Cadence for test insertion, pattern generation and verification.

Aufgaben

• Develop DFT specifications and drive flow and methodology enhancements.
• Implement and validate full-chip and block level DFT test structures such as JTAG, IJTAG, Scan & compression, IEEE1500, LBIST, MBIST, IP tests etc.
• Generate & simulate test patterns, analyze & improve test coverage.
• Write and verify test mode timing constraints.
• Close cooperation with SoC and Physical Design teams to improve testability, meet coverage requirements and integrate DFT implementations.
• Work with test engineers to bring up test patterns on silicon and debug yield problems.
• Guide junior engineers.

Kenntnisse

DFT techniques

JTAG

LBIST

Scripting TCL/Python

Test structure design

Ausbildung

Bachelor's/Master's Degree in Electrical Engineering or Information Technology

Tools

Synopsys tools

Mentor tools

Cadence tools

Jobbeschreibung

Extending our international team, we are looking for an experienced DFT Engineer.

Job Description

• Develop DFT specifications and drive flow and methodology enhancements
• Implement and validate full-chip and block level DFT test structures such as JTAG, IJTAG, Scan & compression, IEEE1500, LBIST, MBIST, IP tests etc.
• Generate & simulate test patterns, analyze & improve test coverage
• Write and verify test mode timing constraints
• Close cooperation with SoC and Physical Design teams to improve testability, meet coverage requirements and integrate DFT implementations
• Work with test engineers to bring up test patterns on silicon and debug yield problems
• Guide junior engineers

Requirements

• Bachelor’s/Master’s Degree in Electrical Engineering, Information Technology or similar
• At least 3+ years experience as DFT engineer
• Strong knowledge of state-of-the-art DFT techniques and concepts like
  • Scan test including Compression, On-chip clock controllers, IEEE 1500 core wrapping, LBIST
  • JTAG, Boundary Scan, iJTAG, AC coupled JTAG
  • MBIST including Built-in self-repair
• Deep experience with industry standard DFT tools from Synopsys, Mentor or Cadence for test insertion, pattern generation and verification
• Ability to drive full-chip DFT insertion from concept to post-silicon bring up
• Strong experience in gate-level simulation with and w/o SDF
• Good programming skills in TCL (or another scripting language like Python, Perl, ...)

A Plus Would Be

• Working knowledge of hardware description languages (VHDL or Verilog and SystemVerilog)
• Experience or working knowledge about synthesis constraints (SDC)
• Experience or working knowledge of SERDES, Analog /mixed-signal DFT techniques (like IOBIST, loop-backs etc.)
• Experience in Post Silicon Pattern conversion for Testers, Pattern Bring-up & Debug, Silicon Characterization etc.
• Experience or familiarity in back-end chip design, Timing Closure, CDC flows

Location

• Dresden, Germany
• Frankfurt/Main, Germany

Employment Type

Full-time (up to 40 hours per week)

About Us

Racyics® is Europe’s leading design service provider for mixed-signal system-on-chip design and turnkey services in advanced nodes.

We deliver professional analog, digital and mixed-signal design services tailored to the customers’ needs with focus on realization of complex System-on-Chips in leading edge technology nodes. Our team of more than 100 employees covers the complete chip design process up to system architecture development. Racyics is working for major German and international semi-custom companies both as a service provider and in collaborative partnerships.

Working at Racyics comes with many benefits, including flexible working hours, mobile work, a financial contribution to your childcare costs and great team events.

Contact

Send us a mail with your CV incl. your certificates, transcripts etc. attached to [e-mail]. Please mind that we can only consider attachments in PDF format.