DFT Design Engineer

TSMC - Taiwan Semiconductor Manufacturing Company Limited; München; Vor Ort; EUR 70.000 - 90.000; Vollzeit

Zusammenfassung

TSMC - Taiwan Semiconductor Manufacturing Company Limited is seeking a DFT Lead in Munich, Germany. The role involves defining DFT strategies for complex SoCs and leading a team through the project lifecycle.

The ideal candidate will have at least 5 years of hands-on DFT experience, a Master's in Electrical Engineering, and strong programming skills in Python and TCL.

Join TSMC to work on innovative technologies and contribute to cutting-edge semiconductor solutions.

Qualifikationen

• Master's degree or above in Electrical Engineering or related majors.
• Over 5 years of hands-on experience with DFT and test flow for complex SOCs.
• Strong knowledge of DFT techniques like JTAG, ATPG, and MBIST.
• Experience with Synopsys tools and programming skills in Python/TCL.

Aufgaben

• Define and document the complete DFT strategy for complex SoC.
• Design and maintain DFT flows utilizing commercial EDA tools.
• Lead the insertion of test structures like Scan and MBIST.
• Collaborate with Physical Design teams to resolve DFT-related issues.
• Lead post-silicon validation and diagnose yield issues.

Kenntnisse

DFT techniques

Python programming

TCL programming

Shell scripting

JTAG

ATPG

Logic diagnosis

Ausbildung

Master's degree in Electrical Engineering or related field

Tools

Synopsys DFT Compiler

Tetramax

VCS

Tessent

Modus/Encounter

Jobbeschreibung

Responsibilities

• DFT Architecture & Leadership: Define, architect, and document the complete DFT strategy for complex SoC. Lead and mentor a team of DFT engineers throughout the project lifecycle.
• Flow Development: Design, implement, and maintain DFT flows utilizing Synopsys (DFTMAX, TetraMAX, PrimeShield) and Siemens Tessent (Tessent Shell, TestKompress) toolsets.
• iJTAG Integration: Serve as the internal expert on iJTAG (IEEE 1687). Architect and implement hierarchical iJTAG networks, instrument connectivity, and ICL/PDL description generation for IP block integration.
• Implementation: Drive the insertion of Scan, MBIST (Memory Built-In Self-Test), LBIST, and Analog Macro test structures.
• ATPG & Verification: Generate and validate high-quality ATPG patterns (stuck-at, transition fault, path delay, and cell-aware). Perform extensive pre-silicon DFT verification at both block and full-chip levels using gate-level simulations (GLS) with timing.
• Physical Design Collaboration: Work closely with the Synthesis and Physical Design teams to resolve DFT-related timing closure, routing congestion, and power issues.
• Silicon Bring-up & Diagnostics: Lead post-silicon validation, ATE (Automatic Test Equipment) deployment, and debug activities to diagnose yield issues and silicon failures.

Qualifications

• Master's degree or above in Electrical Engineering or any other related majors.
• Over 5 years of experience of hands‑on experience with DFT and test flow with commercial EDA tools for large and complex SOCs.
• Strong fundamental knowledge of DFT techniques include JTAG, ATPG, yield learning, logic diagnosis, Scan compression, IEEE 1500 Std. and MBIST.
• Experience with Synopsys DFT Complier, Tetramax and VCS is required. Experience with Tessent and Modus/Encounter tool suite is a plus.
• Strong programming skills in Python/TCL and shell scripting is required.