Senior Principal Design Engineer

Jobtailor; München; Vor Ort; EUR 120.000 - 170.000; Vollzeit

Zusammenfassung

Cadence Technologies is seeking a senior engineering leader to drive silicon programs from design synthesis through tapeout, collaborating with Cadence R&D to advance tools and methodologies. The role focuses on achieving aggressive power, performance and area goals and mentoring engineers across the EMEA region.

You will engage with customers and senior leadership to communicate technical results, influence design directions and contribute to pre-sales efforts, spanning RTL-to-GDSII flows,

Qualifikationen

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related discipline.
• 15+ years of relevant semiconductor engineering experience, or equivalent demonstrated technical achievement.
• Proven tape-out experience on advanced process nodes.
• Experience with leading-edge CPUs, GPUs, AI/ML accelerators, networking devices, or other high-performance SoCs.
• Extensive experience developing and delivering complex semiconductor products.
• Deep expertise in one or more areas of the semiconductor implementation flow, with broad understanding of the SoC development lifecycle.
• Experience with advanced process technologies and complex physical implementation challenges.
• Ability to diagnose and solve problems across traditional functional boundaries.
• Experience working directly with semiconductor customers, foundries, or technology partners.
• Excellent technical communication and presentation skills.
• Ability to influence technical direction without relying solely on organisational authority.
• Technical team leadership experience essential.
• Excellent oral and written English essential.
• Self-motivated with excellent planning, interpersonal, and communication skills.

Aufgaben

• Provide technical leadership for silicon programs from synthesis to tapeout.
• Develop methodologies to improve power, performance and area.
• Collaborate with Cadence R&D to influence tool development.
• Lead technical investigations into silicon failures and convergence challenges.
• Mentor implementation engineers as a technical authority.
• Present results to senior leadership and customers.
• Assist with pre-sales support and effort estimation.
• Work across RTL-to-GDSII flows, timing, power, signal integrity, and integration.

Kenntnisse

Technical leadership

English communication

Mentoring engineers

Presentation skills

Planning skills

Ausbildung

Bachelor's or Master's in Electrical/Computer Engineering

Tools

Cadence Technologies

Cadence R&D Tools

Automation Tools

RTL-to-GDSII Flows

Jobbeschreibung

• Provide technical leadership for complex, high-visibility silicon programs from synthesis/netlist through physical implementation, signoff, and tapeout


• Develop and deploy advanced methodologies to achieve aggressive power, performance, and area objectives


• Work with the PSG engineering team to understand design implementation challenges and develop practical solutions


• Collaborate with Cadence R&D to identify product gaps, influence tool development, and drive enhancements for advanced silicon designs


• Drive technical innovation across physical design, timing, power, signal integrity, physical verification, and signoff with the PSG European team


• Evaluate and introduce Cadence technologies, methodologies, and IP into customer design flows


• Lead technical investigations into silicon failures, performance limitations, convergence challenges, and methodology issues


• Establish reusable methodologies and best practices across customers and technology nodes


• Mentor and develop implementation engineers as a technical authority within the PSG EMEA organisation


• Represent Cadence as a technical thought leader with strategic customers, partners, and the semiconductor ecosystem


• Present technical results and innovations to senior leadership, customers, industry forums, and engineering communities


• Assist with pre-sales support information and effort estimation alongside the Design Engineering Director and Sales team


• Work across advanced-node digital implementation, RTL-to-GDSII flows, physical design and optimisation, timing closure and signoff, power optimisation and analysis, signal integrity and electromigration, SoC integration, IP integration, DTCO, advanced packaging, and automation/methodology development including AI acceleration

Requirements

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related discipline


• 15+ years of relevant semiconductor engineering experience, or equivalent demonstrated technical achievement


• Proven tape-out experience on advanced process nodes


• Experience with leading-edge CPUs, GPUs, AI/ML accelerators, networking devices, or other high-performance SoCs


• Extensive experience developing and delivering complex semiconductor products


• Deep expertise in one or more areas of the semiconductor implementation flow, with broad understanding of the complete SoC development lifecycle


• Experience with advanced process technologies and complex physical implementation challenges


• Ability to diagnose and solve problems across traditional functional boundaries


• Experience working directly with semiconductor customers, foundries, or technology partners


• Excellent technical communication and presentation skills


• Ability to influence technical direction without relying solely on organisational authority


• Technical team leadership experience essential


• Excellent oral and written English essential


• Self-motivated with excellent planning, interpersonal, and communication skills

Core Competencies

Demonstrates extensive expertise in semiconductor engineering, with a focus on advanced process technologies, physical design, and SoC integration. Proven ability to lead technical teams, mentor engineers, and influence design methodologies while effectively communicating complex technical concepts.

Highest-signal resume keywords

• Silicon Program Leadership


• Advanced Process Technologies


• Tape-Out Experience


• Technical Team Leadership


• SoC Development Lifecycle

ATS Optimization Keywords

Hard Skills

• Physical Design


• Timing Closure


• Power Optimisation


• Signal Integrity


• Electromigration


• RTL-to-GDSII Flows


• AI/ML Accelerators


• Complex Semiconductor Products


• Methodology Development


• DTCO

Soft Skills

• Technical Communication


• Interpersonal Skills


• Self-Motivated


• Planning Skills
  
• Presentation Skills

Industry Keywords

• Semiconductor Engineering


• High-Performance SoCs


• Advanced-Node Digital Implementation


• Physical Verification


• Customer Engagement

Tools & Technologies

• Cadence Technologies


• Cadence R&D Tools


• Automation Tools


• Design Flows


• Customer Design Flows