Sr Principal Design Engineer

Cadence; Feldkirchen; Vor Ort; EUR 120.000 - 180.000; Vollzeit

Benefits dieser Stelle

Travel: 10%

Zusammenfassung

Cadence is seeking a Senior Principal Digital Implementation Engineer to lead advanced-node silicon programs and guide implementation teams. You will apply deep expertise in silicon implementation, EDA methodologies, and patient leadership to deliver high-performance, power-efficient designs.

You will collaborate with Cadence R&D and customers, driving tool development, methodology improvements, and efficient design flows.

Qualifikationen

• Bachelor's or Master’s degree in Electrical or Computer Engineering or related discipline.
• 15+ years of semiconductor engineering experience or equivalent.
• Proven tape-out experience on advanced process nodes.
• Experience with CPUs, GPUs, AI/ML accelerators, networking devices or high-performance SoCs.
• Strong leadership and ability to mentor engineers.

Aufgaben

• Provide technical leadership for complex, high-visibility silicon programs from synthesis to tapeout.
• Develop and deploy advanced methodologies to achieve aggressive PPA objectives.
• Collaborate with design teams and Cadence R&D to drive tool enhancements.
• Lead technical investigations and establish reusable methodologies across customers and tech nodes.
• Present results to senior leadership, customers, and industry forums.

Kenntnisse

Silicon implementation

Tape‑out experience

CPUs/GPUs/AI accelerators

Team leadership

Technical communication

Customer engagement

EDA methodologies

Electrical/Computer engineering

Ausbildung

Bachelor's or Master's degree in Electrical or Computer Engineering

Jobbeschreibung

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.

Job Title: Senior Principal Digital Implementation Engineer

Location: Cork, Munich, Katowice, Edinburgh

Reports to: Design Engineering Director

The Role

We are seeking an exceptional Senior Principal Engineer to provide technical leadership on some of the industry's most challenging silicon development programs. In this role, you will apply deep expertise in silicon implementation and advanced EDA methodologies to solve problems and deliver results. You will work directly with strategic customers and internal Cadence teams to develop, deploy, and demonstrate innovative methodologies for advanced-node designs. This is a hands‑on technical leadership role. The successful candidate will combine outstanding semiconductor engineering expertise with the ability to influence lead a team of implementation engineers and technically contribute to architecture, methodology, tool development, and customer strategy.

Key Responsibilities

• Provide technical leadership for complex, high‑visibility silicon programs, Synthesis/Netlist through physical implementation, signoff, and tapeout.
• Develop and deploy advanced methodologies for achieving aggressive power, performance, and area (PPA) objectives.
• Work closely within the PSG engineering team to understand design implementation challenges and translate them into practical solutions.
• Collaborate directly with Cadence R&D to identify product gaps, influence tool development, and drive enhancements required for advanced silicon designs.
• Drive technical innovation across physical design, timing, power, signal integrity, physical verification, and signoff with the PSG European team
• Evaluate and introduce new Cadence technologies, methodologies, and IP into customer design flows.
• Lead technical investigations involving difficult silicon failures, performance limitations, convergence challenges, or methodology issues.
• Establish reusable methodologies and best practices that can be deployed across multiple customers and technology nodes.
• Mentor and develop our implementation engineers, serving as a technical authority within the PSG EMEA (Europe) organisation.
• Represent Cadence as a technical thought leader with strategic customers, partners, and the wider semiconductor ecosystem.
• Present technical results and innovations to senior leadership, customers, industry forums, and engineering communities.
• Assist in the preparation of pre‑sales support information and effort estimation with the Design Engineering Director and Sales team

Technical Scope

Depending On Experience, The Role May Encompass Areas Including

• Advanced-node digital implementation
• RTL-to-GDSII flows
• Physical design and optimisation
• Timing closure and signoff
• Power optimisation and analysis
• Signal integrity and electromigration
• SoC integration and hierarchical implementation within a layout team
• IP integration and reuse
• Process/design technology co‑optimization (DTCO)
• Advanced packaging
• Automation and methodology development including AI acceleration.

Required Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related discipline.
• 15+ years of relevant semiconductor engineering experience, or equivalent demonstrated technical achievement.
• Proven tape‑out experience on advanced process nodes.
• Experience working with leading‑edge CPUs, GPUs, AI/ML accelerators, networking devices, or other high‑performance SoCs.
• Extensive experience developing and delivering complex semiconductor products.
• Deep expertise in one or more areas of the semiconductor implementation flow, combined with broad understanding of the complete SoC development lifecycle.
• Demonstrated experience with advanced process technologies and complex physical implementation challenges.
• Proven ability to diagnose and solve problems that cross traditional functional boundaries.
• Experience working directly with semiconductor customers, foundries, or technology partners.
• Excellent technical communication and presentation skills.
• Demonstrated ability to influence technical direction without relying solely on organisational authority.
• Experience of Technical Team leadership essential
• Excellent oral and written English essential
• Self‑motivated with excellent planning, interpersonal, and communication skills

What Success Looks Like

• A successful Senior Principal Engineer will:
• Solve the problems others cannot. Take ownership of technically ambiguous, high‑impact problems and drive them to resolution.
• Enable customer success. Become a trusted technical partner to leading semiconductor companies and help them achieve ambitious silicon objectives.
• Create leverage. Turn solutions developed for individual programs into reusable methodologies, tools, and engineering practices.
• Lead through expertise. Raise the technical capability of the wider engineering organisation through mentoring, collaboration, and technical leadership.

Why Join the PSG Team?

• This is an opportunity to work at the intersection of advanced semiconductor technology, EDA, and real silicon.
• You will work on problems that are often at the limits of what current design methodologies and technologies can achieve, collaborating with some of the world's leading semiconductor companies and technology partners.
• Rather than being limited to a single product or stage of the design flow, you will have the opportunity to influence the entire path from technology and methodology through to working silicon.
• If you are an engineer who wants to solve the industry's hardest silicon problems—and see those solutions become real products—this is the team for you.

Additional Information

Cadence is committed to equal employment opportunity and employment equity throughout all levels of the organization. We strive to attract a qualified and diverse candidate pool and encourage diversity and inclusion in the workplace.

Travel: 10%

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