IP Methodology & Design Flow Engineer

TSMC - Taiwan Semiconductor Manufacturing Company Limited; München; Vor Ort; EUR 120.000 - 190.000; Vollzeit

Zusammenfassung

TSMC in Munich seeks an experienced engineer to lead IP design flow and methodology development. You will design, build, and support unified front-to-back flows for mixed-signal IP, bridging analog schematic/layout with digital implementation and enforcing best practices for IP reuse and modularity.

Responsibilities include AMS verification, timing sign-off, and IP packaging. You will work with Cadence Virtuoso, Synopsys tools, and scripting (Python/Tcl) to automate validation and ensure robust

Qualifikationen

• Master’s degree in electrical or related field required.
• 10+ years of CAD/design methodology or IP development experience.
• Strong experience with mixed-signal front-to-back flows.

Aufgaben

• Design, build and maintain unified IP design flows from front to back.
• Develop AMS verification methodologies and co-simulation strategies.
• Define timing closure methodologies for mixed-signal interfaces.
• Automate design tasks with Python/Tcl/SKILL for regression testing.
• Define standard IP packaging and release processes.

Kenntnisse

CAD automation

AMS verification

Scripting languages

Ausbildung

Master’s degree in Electrical/Computer Engineering or related field

Tools

Cadence Virtuoso

Synopsys Design Compiler

PrimeTime

Genus/Innovus

Xcelium

AMS Designer

Jobbeschreibung

IP Design Flow & Methodology Development

1. Design, build, and support unified front-to-back design flows for mixed-signal IP development, bridging analog schematic/layout environments with digital implementation environments
2. Define and enforce best practices for IP reuse, modularity, and multi-process node portability

Mixed-Signal Verification & Modeling

1. Establish robust Analog/Mixed-Signal (AMS) verification methodologies to enable automated, top-level co-simulations
2. Standardize and automate the generation of high-quality behavioral models to enable early system-level simulations for IP consumers

Interface Timing & Sign-Off

1. Define methodologies for timing closure across analog-digital IP interfaces, including Static Timing Analysis (STA) on mixed-signal boundaries and constraint generation
2. Build and automate physical verification sign-off flows (DRC/LVS/PEX, EM/IR drop, and reliability analysis) tailored for IP integration

CAD Automation & Scripting

1. Develop and maintain robust automation scripts (Python, Tcl, SKILL, Perl) to minimize human error, automate repetitive design tasks, and accelerate regression testing

IP Packaging & Release Management

1. Define standard IP delivery packages (including Liberty files/lib, LEF/GDS, CDL, behavioral models, and integration guidelines)
2. Manage design data, workspaces, and IP version control utilizing configuration management systems

Qualifications

• Education: Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• Experience: 10+ years of experience in CAD, design methodology, or IP development (analog, digital, or mixed-signal).
• Mixed‑Signal Flow Expertise: Strong hands‑on experience with industry‑standard EDA environments.
• Analog/Custom: Cadence Virtuoso (ADE, Spectre), Synopsys Custom Compiler.
• Digital Front/Back‑End: Synopsys Design Compiler/PrimeTime, Cadence Genus/Innovus.
• Mixed‑Signal Verification: Cadence Xcelium/AMS Designer, Synopsys VCS/XA.
• Scripting Skills: Proficiency in scripting languages used in modern EDA flows (Tcl, Python, SKILL, Shell scripting).
• IP‑Specific Knowledge: Deep understanding of IP packaging, process design kits (PDKs), physical extraction (PEX/EM/IR), and boundary timing constraints.